Clock signal generation circuit having detective circuit detecti

Details Clock signal generation circuit having detective circuit detecti Clock signal generation circuit having detective circuit detecti

1994-10-27

1996-10-01

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327156, 327 20, H03L 706

Patent

active

055613900

ABSTRACT:
A clock signal generation circuit is disclosed which receives a reference clock and detects, in response thereto, the loss of the reference clock. A phase comparator 13, detects the phase difference between the reference clock signal and an stabilized clock from a PLL synthesizer, a signal DOWNB state of the phase comparator 13 is fixed to "0" level at the time of loss of the reference clock signal where the reference clock can be fixed to "0" or "1" level. The signal DOWNB is monitored using a reference clock loss detection circuit 12. If the signal DOWNB stays at the "0" level for a prescribed length of time, the reference clock loss detection circuit 12 judges that the reference clock is lost and brings an XTALFAIL signal to the active state.

REFERENCES:
patent: 4791386 (1988-12-01), Shiga
patent: 5008635 (1991-04-01), Hanke et al.
patent: 5126690 (1992-06-01), Bui et al.
patent: 5128632 (1992-07-01), Erhart et al.
patent: 5208546 (1993-05-01), Nagaraj et al.
patent: 5304953 (1994-04-01), Heim et al.
Den Dulk, R. C., Digital PLL Lock-Detection Circuit, Electronics Letters, 1988, vol. 24, No. 14, pp. 880-882.

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