Electrical pulse counters – pulse dividers – or shift registers: c – Starting – stopping – presetting or resetting the counter – Counter chains with a radix or base other than the number...
Patent
1995-02-02
1996-03-12
Heyman, John S.
Electrical pulse counters, pulse dividers, or shift registers: c
Starting, stopping, presetting or resetting the counter
Counter chains with a radix or base other than the number...
377 48, 327115, H03K 2348
Patent
active
054992800
ABSTRACT:
The clock signal generator of the present invention divides a higher frequency clock down to a frequency that is an uneven sub-multiple of the higher frequency. The input clock to be divided down clocks an 11-bit counter (105-110) that outputs an overflow signal to a D flip-flop (125). The D flip-flop generates a load signal that resets the counter after 1025 clock periods. The load signal also suppresses, after 1025 clock periods, the toggling of another toggle flip-flop (120) that provides a divide by two clock. By suppressing a clock pulse in the divide by two clock, every 1025 clock pulses of the higher frequency clock, the average clock frequency of the divide by two clock is reduced to an uneven sub-multiple of the higher clock frequency.
REFERENCES:
patent: 4573176 (1986-02-01), Yeager
patent: 4942595 (1990-07-01), Baca
patent: 5077764 (1991-12-01), Yamashita
patent: 5365119 (1994-11-01), Kivari
patent: 5371772 (1994-12-01), Al-Khairi
patent: 5390223 (1995-02-01), Lindholm
McAllister Gene H.
Wilson Nathaniel B.
Heyman John S.
Martin Roger W.
Miller Russell B.
Qualcomm Incorporated
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