Clock signal generating device having a redundant configuration

Details Clock signal generating device having a redundant configuration Clock signal generating device having a redundant configuration

1996-09-26

1999-03-16

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

375376, H03L 706, H04L 700

Patent

active

058835334

ABSTRACT:
A clock signal generating device of the present invention has an active and a spare clock selecting circuit. The two clock selecting circuits each includes a selector for selecting one of a plurality of outside timing signals and outputting it as an inside clock signal under the control of a controller. A PLL (Phase Locked Loop) circuit is commonly connected to the outputs of the active and spare selecting circuits. The PLL circuit reduces the influence of switching between the active and spare selecting circuits and switching between the outside timing signals. The PLL circuit includes a hold-over circuit for temporarily holding, in response to a control signal fed from the controller, a signal output from the selecting circuit.

REFERENCES:
patent: 5194828 (1993-03-01), Kato et al.
patent: 5455840 (1995-10-01), Nakauchi et al.
patent: 5497126 (1996-03-01), Kosiec et al.
patent: 5574757 (1996-11-01), Ogawa
patent: 5673004 (1997-09-01), Park
patent: 5682112 (1997-10-01), Fukushima

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