Oscillators – Electrical noise or random wave generator
Reexamination Certificate
2003-01-30
2004-09-28
Kinkead, Arnold (Department: 2817)
Oscillators
Electrical noise or random wave generator
C331S018000, C327S008000, C327S153000, C327S158000, C327S159000, C375S213000
Reexamination Certificate
active
06798303
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention relates to a clock signal generating device having an oscillator and a PLL connected downstream thereof.
Such a clock signal generating device is illustrated in FIG.
1
. In this case, the oscillator is designated by the reference symbol OSC, and the PLL (phase-locked loop) is designated by the reference symbol PLL. The PLL contains a phase detector or phase comparator PD, a loop filter LF, a voltage-controlled oscillator VCO and a frequency divider DIV, which are connected in the manner shown in FIG.
1
.
A PLL generally serves for generating a clock signal having a frequency that differs from the frequency of the signal output by the oscillator OSC, and more precisely, for generating a clock signal having a frequency that is greater than the frequency of the signal output by the oscillator OSC by a specific factor.
The clock signal output by the PLL is generated by the voltage-controlled oscillator VCO. In other words, the output signal of the voltage-controlled oscillator VCO is at the same time the output signal of the configuration shown in FIG.
1
. The output signal of the voltage-controlled oscillator VCO is furthermore fed to the frequency divider DIV. The frequency divider DIV generates a signal whose frequency is a specific factor less than the frequency of the signal fed to it. The factor is chosen such that, when the frequency of the signal generated by the voltage-controlled oscillator VCO is the desired frequency sought, the frequency of the output signal of the frequency divider DIV corresponds precisely to the frequency of the signal output by the oscillator OSC. The output signal of the frequency divider DIV is fed to the phase comparator PD. In addition, the signal output by the oscillator OSC is fed to the phase comparator PD. The phase comparator PD compares the phases, more precisely the position of the edges of the signals fed to it, and outputs signals charge and discharge, which depend on the phase difference. These signals are fed to the loop filter LF, which converts them into a drive signal for the voltage-controlled oscillator VCO. The conversion is effected in such a way that the voltage-controlled oscillator VCO is caused to maintain its instantaneous frequency if the phase difference is equal to zero, and to alter the frequency if the phase difference is not equal to zero.
If the phase difference is equal to zero, the PLL is said to be locked on. The PLL runs stably from then on since deviations between the frequency of the signal output by the voltage-controlled oscillator VCO and the desired frequency are immediately corrected on account of the resultant relative phase shift between the signals fed to the phase comparator.
Although the frequency of the clock signal generated by the configuration shown in
FIG. 1
is generally always precisely the desired frequency, the use of this clock signal can lead to problems in practice. This is because the electrical circuits which operate using such a clock signal generate huge electromagnetic emissions. It is particularly undesirable that particularly strong emissions are produced in this case at a few frequencies. The frequency spectra of the electromagnetic emissions clearly discernibly show the clock harmonics as main interference frequencies.
Although electromagnetic emissions can never be entirely prevented, it would be more favorable in many cases if the interference were at least distributed somewhat more uniformly over a larger frequency range.
This can be achieved for example by varying the frequency of the clock signal generated by the clock signal generating device, that is to say by generating a frequency-modulated clock signal.
The effects that can thereby be achieved are illustrated in FIG.
2
.
FIG. 2
illustrates, on the left-hand side, the profile of different clock signals and, in each case on the right beside the latter, the frequency spectrum of the relevant clock signal.
The conditions for five different clock signals are illustrated, to be precise:
right at the top for a clock signal with a constant frequency f1;
below that for a clock signal with a constant frequency f2;
below that for a clock signal with a constant frequency f3;
below that for a clock signal with a constant frequency f4; and
right at the bottom for a clock signal with a frequency that varies between f1 and f4.
As can be seen from the designation of the last-mentioned clock signal, i.e. the clock signal with a varying frequency, the clock signal is composed of periods or period parts of the clock signals with the constant frequencies f1 to f4, that is to say, it is the result of a staircase-type modulation.
As can be seen from the illustration of the frequency spectra in
FIG. 2
, the frequency spectrum of the clock signal with a varying frequency has the smallest maximum value. This maximum value is illustrated by a reference line B. The maximum values of the frequency spectra for the clock signals with a constant frequency f1 and f2 and f3 and f4, respectively, are considerably greater by comparison therewith. Although extreme values occur at a larger number of frequencies in the case of the clock signal with a varying frequency, a distribution of the energy between a plurality of frequencies or a larger frequency range can generally be tolerated without difficulty. For the sake of completeness, it should be noted in this connection that the energy for a continuous modulation signal is distributed over a frequency range that is proportional to the modulation swing.
The effects and possibilities for generating a clock signal with a varying frequency that can be obtained through a clock signal with a varying frequency are known, for example, from the following documents:
[1] EP 0 655 829 A1;
[2] EP 0 739 089 A2;
[3] WO 00/21237 A1;
[4] Keith B. Hardin et al: Spread Spectrum Clock Generation for the Reduction of Radiated Emissions, 1994 IEEE International Symposium On Electromagnetic Compatibility;
[5] Keith B. Hardin et al: A Study of the Interference Potential of Spread Spectrum Clock Generation Techniques, 1995 IEEE International Symposium On Electromagnetic Compatibility; and
[6] Keith B. Hardin et al: Design Considerations of Phase-Locked Loop Systems for Spread Spectrum Clock Generation Compatibility, 1997 IEEE International Symposium On Electromagnetic Compatibility.
Using clock signals with a varying frequency is designated by the technical term “spread spectrum clocking”. Clock signal generating devices which generate clock signals with a varying frequency are designated by the technical term “spread spectrum oscillators”.
Spread spectrum oscillators are already known. A known spread spectrum oscillator is shown in FIG.
3
.
The spread spectrum oscillator shown in
FIG. 3
contains an oscillator OSC, a phase-locked loop PLL, a counter CNT, a memory device MEM, formed for example, by a ROM, a D/A converter DAC, a summation element SUM, and a second voltage-controlled oscillator VCO
2
.
The oscillator OSC and the phase-locked loop PLL are the oscillator OSC and the phase-locked loop PLL of the clock signal generating device shown in FIG.
1
. With regard to further details in respect thereof, reference is made to the explanations with reference to FIG.
1
.
The counter CNT receives, as an input signal, the clock signal output by the oscillator OSC and outputs the count to the memory MEM. The memory MEM uses the count output by the counter CNT as an address and outputs the data stored under this address to the D/A converter DAC. The D/A converter subjects the data fed to it to a D/A conversion and outputs the result of this D/A conversion to the summation element SUM. Furthermore, the output signal of the loop filter LF of the phase-locked loop PLL is also fed to the summation element SUM. The summation element sums the signals fed to it and outputs the resultant signal as a control signal to the second voltage-controlled oscillator VCO
2
.
The clock signal generated by the s
Hesidenz Dirk
Steinecke Thomas
Kinkead Arnold
Locher Ralph E.
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