Clock signal generating circuit using variable delay circuit

Details Clock signal generating circuit using variable delay circuit Clock signal generating circuit using variable delay circuit

1997-12-23

1999-11-23

Wells, Kenneth B.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327158, 327162, 327277, H03L 706

Patent

active

059907142

ABSTRACT:
In an high-frequency LSI chip, a clock signal generating circuit establishes accurate synchronization between an input clock signal and an internal clock signal to prevent an input circuit from causing a synchronization shift. The clock signal generating circuit includes an input circuit for amplifying an input signal and outputting in amplified signal as a first internal signal; a variable delay circuit, on the basis of a control signal, for delaying the first internal signal and outputting a delayed signal as a second internal signal; a phase comparator for finding a phase difference between the input signal and second internal signal and outputting a phase difference signal indicative of the phase difference; and a control circuit for generating the control signal on the basis of the phase difference signal. Thus, the influences of a delay caused by the input circuit, which would not be avoided in the prior art, can be avoided and the accurate internal clock signal can be generated.

REFERENCES:
patent: 5087829 (1992-02-01), Ishibashi et al.
patent: 5764092 (1998-06-01), Wada et al.
patent: 5790612 (1998-08-01), Chengson et al.
patent: 5852380 (1998-12-01), Yamauchi

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