Clock signal generating circuit for television receiver

Facsimile and static presentation processing – Facsimile – Specific signal processing circuitry

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Details

358150, 358153, 358158, 331 20, 307516, 375118, 375120, H04N 504, H04N 506

Patent

active

048090689

ABSTRACT:
A clock signal generating circuit for a television receiver, which generates a composite synchronizing signal and a masking signal for controlling the operation of the circuit, the composite synchronizing signal including at least two partial signals. The circuit includes a voltage controlled oscillator for generating an output oscillation signal having a predetermined frequency, a source for supplying a reference voltage corresponding to a predetermined center frequency of the oscillation signal to the oscillator, a phase comparator for comparing the phase of the oscillation signal output from the oscillator with the phase of one of the two partial signals and generating a phase error signal corresponding to the difference in phase between the oscillation signal and the one of the two partial signals for adjusting the frequency of the oscillation signal, a circuit responsive to the masking signal for interrupting the comparison by the phase comparator for a period of time corresponding to the period of another one of the two partial signals, a switch for interrupting the supply of the reference voltage to the oscillator during the period when the mask circuit is interrupting the comparison, and a device for maintaining the voltage supplied to the oscillator at a level corresponding to the voltage supplied at the time of the interruption by the switch and the mask circuit.

REFERENCES:
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patent: 4228463 (1980-10-01), Steckler et al.
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patent: 4253116 (1981-02-01), Rodgers, III
patent: 4488103 (1985-02-01), Aschwanden
patent: 4647970 (1987-03-01), Sumiyoshi
patent: 4660080 (1987-04-01), Dietz et al.
patent: 4729024 (1988-03-01), Kawai et al.

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