Clock signal generating circuit for dynamic type semiconductor m

Details Clock signal generating circuit for dynamic type semiconductor m Clock signal generating circuit for dynamic type semiconductor m

1986-08-07

1988-04-19

Fears, Terrell W.

Static information storage and retrieval

Addressing

Sync/clocking

365154, 365189, G11C 1300

Patent

active

047395028

ABSTRACT:
A clock signal generating circuit for a dynamic type semiconductor memory device including an input voltage level control unit for converting a transistor-transistor-logic (TTL) drive level to a metal-oxide-semiconductor (MOS) drive level during transmission of an address strobe signal; an address buffer control unit for generating an address signal and an inverted address signal in response to a trailing edge of the address strobe signal, a clock signal generating unit for generating a clock signal used for a word line selection and an input signal for a next stage in response to a low level of the address strobe signal, and an inhibiting unit for inhibiting a drive of the word line by the clock signal when the address strobe signal is at high level in the timing of a leading edge of the clock signal.

REFERENCES:
patent: 4562555 (1985-12-01), Ouchi et al.

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