Clock signal generating circuit and semiconductor memory...

Details Clock signal generating circuit and semiconductor memory... Clock signal generating circuit and semiconductor memory...

2011-03-22

2011-03-22

Luu, An T (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S063000, C327S299000

Reexamination Certificate

active

07911251

ABSTRACT:
A clock signal generating circuit includes a main clock buffering unit and a sub clock buffering unit. The main clock buffering unit is capable of generating both a differential clock signal pair and a single clock signal. The main clock buffering unit selectively outputs either the differential clock signal pair or the single clock signal depending upon the frequency of an external clock signal. The sub clock buffering unit receives the output of the main clock buffering unit and generates first and second clock signals. The operation of the sub clock buffering unit depends upon whether the differential clock signal pair or the single clock signal is output by the main clock buffering unit.

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patent: 2006-060842 (2006-03-01), None
patent: 1020060046024 (2006-05-01), None

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