Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Reexamination Certificate
2000-03-27
2001-11-27
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Clock or pulse waveform generating
C327S116000, C327S119000
Reexamination Certificate
active
06323713
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a clock signal generating circuit for generating a clock signal.
2. Description of Related Art
In an apparatus such as communication equipment which needs a clock signal of high frequency precision, a device of high frequency precision is used as an oscillating circuit (for example, quartz oscillator) serving as a source to generate the clock signal.
Since the oscillating circuit of high frequency precision, however, is expensive, it has a problem that a product price also rises in accordance with it.
OBJECTS AND SUMMARY OF THE INVENTION
The invention has been made to solve the problem and it is an object of the invention to provide a clock signal generating circuit, which can generate a clock signal of a desired frequency even if an oscillating circuit of relatively low frequency precision is used, and to provide its clock frequency adjusting method.
According to the invention, there is provided a clock signal generating circuit for generating a clock signal of a frequency obtained by dividing a frequency of a constant frequency signal comprising: a memory in which a plurality of frequency division data has been stored; a memory control circuit for providing control so as to sequentially and repetitively read out each of the frequency division data stored in the memory; a frequency dividing counter for obtaining a count value by counting the number of pulses of the constant frequency signal and resetting the count value to an initial value when the count value coincides with the frequency division data read out from the memory; and a circuit for forming a signal whose logic level is inverted each time the frequency division data read out from the memory and the count value coincide, and generating it as a clock signal.
According to a clock frequency adjusting method of the invention, when the frequency of the constant frequency signal is lower than a desired request frequency, a value of at least one of the frequency division data stored in the memory is decreased, and when the frequency of the constant frequency signal is higher than the desired request frequency, a value of at least one of the frequency division data stored in the memory is increased.
According to the invention, each of the frequency division data is sequentially and repetitively read out from the memory in which the plurality of frequency division data has been stored and the signal whose logic level is inverted each time the read-out frequency division data coincides with the number of pulses of the constant frequency signal generated by an oscillating circuit is generated as a clock signal. By performing an adjustment, therefore, so as to decrease the value of at least one of the frequency division data stored in the memory when the frequency of the constant frequency signal is lower than the desired request frequency and to increase the value of at least one of the frequency division data stored in the memory when the frequency of the constant frequency signal is higher than the desired request frequency, even if the frequency precision of the oscillating circuit is low, the clock signal of a desired frequency which satisfies the request precision can be generated.
REFERENCES:
patent: 3798564 (1974-03-01), Langham
patent: 3970954 (1976-07-01), Even
patent: 03085012 (1991-04-01), None
patent: 04100310 (1992-04-01), None
patent: 05129895 (1993-05-01), None
OKI Electric Industry Co., Ltd.
Rabin & Berdo P.C.
Wells Kenneth B.
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