Clock signal generating circuit

Details Clock signal generating circuit Clock signal generating circuit

1995-09-27

1998-02-10

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327236, 327155, 327161, H03L 706, H03K 5159

Patent

active

057173532

ABSTRACT:
A phase-synchronizing type clock signal generating circuit including a DLL (delay line loop) circuit, capable of performing a similar operation for a DLL circuit even under the low-speed operation as in the high-speed operation. The clock signal generating circuit includes: a delay circuit for delaying an internal clock signal upon receipt of a reference clock signal externally provided; a selector circuit which selects and outputs either the reference clock signal or an output from the delay circuit, in accordance with a selector signal externally provided; a buffer circuit which delays the internal clock signal for as long as a signal passing delay time duration for the selector circuit; and a delay line loop which delays the reference clock signal upon receipt of an output signal from the selector circuit and that from the buffer circuit.

REFERENCES:
patent: 4495468 (1985-01-01), Richards et al.
patent: 4603298 (1986-07-01), Malka et al.
patent: 4922141 (1990-05-01), Lofgren et al.
patent: 5126693 (1992-06-01), Gulliver et al.
patent: 5399995 (1995-03-01), Kardontchik et al.
patent: 5486783 (1996-01-01), Baumert et al.

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