Clock signal generating circuit

Details Clock signal generating circuit Clock signal generating circuit

1997-08-01

1998-10-06

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Phase shift by less than period of input

327239, H03K 515

Patent

active

058182756

ABSTRACT:
Clock signal generating circuit for preventing occurrence of clock skew, totally preventing through current, and readily controlling the clock, which includes a master clock signal generating circuit 2M and a slave clock signal generating circuit 2S. The master clock signal generating circuit 2M generates a master clock signal MCLK at a high level based on a slave clock signal SCLK at a low level and a clock signal CLK at a low level, and generates a master clock signal MCLK at a low level based on the clock signal CLK at a high level. The slave clock signal generating circuit 2S generates a slave clock signal SCLK at a low level based on the clock signal CLK at a low level and a slave clock signal SCLK at a high level based on the master clock signal MCLK being at a low level and the clock signal CLK at a high level. A master clock delay generating circuit 3M inputs the slave clock signal SCLK as output from the slave clock signal generating circuit 2S to be able to set the delay time optionally in the master clock signal generating circuit 2M by delaying for the necessary time. Additionally, a slave clock delay generating circuit 3S is provided which inputs the master clock signal MCLK output from the master clock signal generating circuit 2M to be able to set the delay time optionally into the slave clock signal generating circuit 2S by delaying for the necessary time.

REFERENCES:
patent: 4283639 (1981-08-01), Roesler
patent: 4417158 (1983-11-01), Ito et al.
patent: 4645947 (1987-02-01), Prak
patent: 4827157 (1989-05-01), Machida et al.
patent: 4894791 (1990-01-01), Jiang et al.
patent: 4905192 (1990-02-01), Nogami et al.
patent: 5041738 (1991-08-01), Walters, Jr.
patent: 5440250 (1995-08-01), Albert
patent: 5453707 (1995-09-01), Hiratsuka et al.
patent: 5517455 (1996-05-01), McClure et al.

Affiliated with

Also associated with

Rating

Clock signal generating circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock signal generating circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock signal generating circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-82485