Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels
Reexamination Certificate
1998-07-07
2002-03-12
Kizou, Hassan (Department: 2662)
Multiplex communications
Communication techniques for information carried in plural...
Combining or distributing information via time channels
C713S400000
Reexamination Certificate
active
06356566
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock signal generating apparatus for a data communication channel which generates a clock signal used for a regenerator section data communication channel and a multiplex section data communication channel for a STM(Synchrnous Transfer Mode)-N system, and in particular, to an improved clock signal generating apparatus for a data communication channel which is capable of generating clock and timing signals used for extracting and inserting an overhead used for a regenerator section data communication channel and a multiplex section data communication channel in a section overhead formed in a STM-N frame structure for a STM-N system for thereby matching the thusly extracted and inserted overhead with an external apparatus.
2. Description of the Conventional Art
In the conventional clock signal generating apparatus for a data communication channel, clock and timing signals used for a data communication channel are generated using 51.8 MHz clock signal. Namely, 51.8 MHz clock signal is divided based on 90- and 180-divides for thereby generating 576 KHz clock signal. In addition, the 51.8 MHz clock signal is divided based on 270- and 540-divides for thereby generating 192 KHz clock signal and its timing signal. In order to generate clock and timing signals, a complicated circuit and a predetermined number of counters which operate at 51.84 MHz are used. Therefore, much electric power is required. In addition, there is a problem in that a timing delay signal generated when processing a high speed 51.8 M-class signal between devices should be accurately compensated.
Furthermore, In case of using 77.76 MHz clock signal in forming a STM-N frame structure for a STM-N system, there are big problems for generating the above-described signals since the timing signals used for a serial/parallel conversion, extraction and insertion of a data for a data communication channel are not integer-time of 77.76 MHz.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a clock signal generating apparatus based on 77.76 MHz clock signal for a data communication channel which overcomes the aforementioned problems encountered in the conventional art.
It is another object of the present invention to provide a clock signal generating apparatus based on 77.76 MHz clock signal for a data communication channel which is capable of implementing a reliable serial/parallel conversion, extraction and insertion of a data by generating a stable clock and timing signal using a simple circuit and supplying a stable clock signal for matching with an external apparatus for thereby achieving a reliable data communication for a system.
It is still another object of the present invention to provide a clock signal generating apparatus based on 77.76 MHz clock signal for a data communication channel which is directed to generating clock and timing signals used for extracting and inserting an overhead used for a regenerator section data communication channel and a multiplex section data communication channel in a section overhead formed in a STM-N frame structure for a STM-N system for thereby matching the thusly extracted and inserted overhead with an external apparatus.
In order to achieve the above objects, there is provided a clock signal generating apparatus based on 77.76 MHz clock signal for a data communication channel which includes a first clock signal generating unit for receiving an external input clock signal and a frame position informing signal and outputting first clock signal having a predetermined cycle and a first timing signal, a second clock signal generating unit for receiving the first clock signal and the first timing signal and externally outputting a first offset signal, a second timing signal, and second clock signal having a predetermined cycle, respectively, and a third clock signal generating unit for receiving the first clock signal and the first timing signal and externally outputting a second offset signal, a third timing signal and cycle third clock signal having a predetermined cycle, respectively.
Additional advantages, objects and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
REFERENCES:
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patent: 5282206 (1994-01-01), Ishihara et al.
patent: 5917818 (1999-06-01), Ko et al.
patent: 5930273 (1999-07-01), Mukojima
Kim Jong Ho
Ko Jeong Hoon
Lee Tae Hee
Lee Yoo Kyoung
Cohen & Pontani, Lieberman & Pavane
Elallam Ahmed
Electronics and Telecommunications Research Institute
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