Clock signal frequency multiplier

Details Clock signal frequency multiplier Clock signal frequency multiplier

1996-08-02

1998-10-13

Ton, My-Trang Nu

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

327107, H03B 1900

Patent

active

058217851

ABSTRACT:
The invention relates to a clock signal frequency multiplier circuit. The circuit multiplies the speed of a clock signal of an integrated circuit (IC) by a factor N to generate a times-N clock signal. The circuit first receives a clock signal. Next, the circuit replicates the clock signal into a plurality of N component signals. Each Jth component signal is delayed from the (J-1)th component signal by 1/N cycles, where J equals 1 to N. The (J=1)th component signal is the clock signal. The N component signals are referred to as phase-shifted components. Finally, the circuit logically combines the phase-shifted components into a times-N clock signal.

REFERENCES:
patent: 5192916 (1993-03-01), Glass
patent: 5220206 (1993-06-01), Tsang et al.
patent: 5359232 (1994-10-01), Eitrheim et al.
patent: 5548235 (1996-08-01), Marbot
patent: 5614841 (1997-03-01), Marbot et al.

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