Clock signal frequency dividing circuit and clock signal...

Details Clock signal frequency dividing circuit and clock signal... Clock signal frequency dividing circuit and clock signal...

2007-11-09

2011-12-20

O'Neill, Patrick (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S117000, C377S047000

Reexamination Certificate

active

08081017

ABSTRACT:
To provide a rational frequency dividing circuit wherein the variations in cycle times of frequency divided clock signals are small, there are many occasions in which the minimum cycle time of frequency divided clock signals and test costs are small. A clock signal frequency dividing circuit, the frequency division ratio of which is specified as N/M where are both N and M are integers, includes an output clock selecting circuit (200) that selects one of three situations: an input clock signal is outputted as it is, the input clock signal is inverted and outputted and the input clock signal is not outputted; and a clock selection control circuit (100) that generates a control signal for controlling the foregoing selection of the output clock selecting circuit. The clock selection control circuit controls the foregoing selection of the output clock selecting circuit at every cycle of the input clock signal.

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International Search Report for PCT/JP2007/071790 mailed Jan. 15, 2008.

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