Clock signal distribution method for reducing active power dissi

Details Clock signal distribution method for reducing active power dissi Clock signal distribution method for reducing active power dissi

1997-07-28

1999-08-17

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

327291, 327299, 327166, H03K 104

Patent

active

059399198

ABSTRACT:
A clocking scheme is provided which uses an external clock signal having a frequency F, and generates an internal master clock signal equal having a frequency lower than (e.g., 1/2) F. The internal master clock signal operating at, for example, half the speed of the external clock is routed throughout a device to components on the device requiring a clock signal (e.g., input or output buffers in a synchronous memory product). A stream of narrow pulses corresponding to rising and falling edges of the internal master clock signal are locally generated for those components which require a clock signal at full frequency. This stream of narrow pulses has a frequency of F.

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patent: 5570054 (1996-10-01), Takla
patent: 5781049 (1998-07-01), Fugo
"Frequency Modulator for Low Power Digital Integrated Circuit Applications," IBM Technical Disclosure Bulletin, vol. 37, No. 11, Nov. 1, 1994, pp. 553-555, XP000487336.

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