Clock signal distribution device

Details Clock signal distribution device Clock signal distribution device

1988-12-13

1989-09-19

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural oscillators controlled

331 55, H03B 2700, H03L 706

Patent

active

048685224

ABSTRACT:
A delay circit is described which automatically adjusts the propagation delay of clock signals, generated by a clock source, distributed to various receiving devices so that the receiving devices are clocked simultaneously. In one embodiment, the clock signal generated by a single clock source is independently delayed for each receiving device. To determine the proper amount of delay, a clock signal is simultaneously transmitted to each of the receiving devices and a clock return signal from each receiving device is returned to a delay circuit via a return path. The delay circuit detects the various differences in round-trip arrival times of the clock signal associated with each receiving device and fixes a particular clock signal delay for each receiving device so that subsequent clock signals will arrive at each receiving device simultaneoulsy.

REFERENCES:
patent: 4411007 (1983-10-01), Rodman et al.
patent: 4497056 (1985-01-01), Sugamori
patent: 4577318 (1986-03-01), Whitacre et al.
M. Johnson et al., "A Variable Delay Line Phase Locked Loop for CPU-Coprocessor Synchronization", IEEE Int. Solid-State Circuits Conference, 1988, pp. 142, 143.

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