Clock signal distribution circuit having a small clock skew

Details Clock signal distribution circuit having a small clock skew Clock signal distribution circuit having a small clock skew

1995-08-30

1997-09-23

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327149, 327156, 327244, H03K 513, H03K 500

Patent

active

056709030

ABSTRACT:
A clock signal distribution circuit provides a synchronized clock signal to a plurality of chips implementing an integrated circuit. The clock signal distribution circuit has a first and a second phase lock loop, a series of voltage controlled delay circuits and a pair of transmission lines formed between the chips. The input clock signal is transmitted from the first chip to the second chip through a transmission line, the end of which is a node supplying the output clock signal to the internal circuit of the second chip. The clock signal is then returned from the output node through the second transmission line. The first phase lock loop controls the series of voltage controlled delay circuits such that the signal at a midpoint reference node has a phase equal to the phase of the output clock signal. The second phase lock loop controls the first voltage controlled delay circuit such that the signal at the first output node has a phase synchronized with the phase of the input clock signal. A plurality of transmission lines with differing delay lengths may be accommodated by bypassing a number of voltage controlled delay circuits, proportional to the delay length of the transmission lines, split equally before the clock output and after the return input.

REFERENCES:
patent: 4881243 (1989-11-01), Whitt
patent: 4922141 (1990-05-01), Lofgren et al.
patent: 5101117 (1992-03-01), Johnson et al.
patent: 5295164 (1994-03-01), Yamamura
patent: 5408200 (1995-04-01), Buhler

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