Clock signal distributing circuit adjusting device and method

Details Clock signal distributing circuit adjusting device and method Clock signal distributing circuit adjusting device and method

1979-12-17

1982-06-29

Miller, Jr., Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307606, 328105, H03K 5159, H03K 1700

Patent

active

043374336

ABSTRACT:
A clock signal distributing circuit is provided in its transmission line with delay time varying means and arranged so that a signal at the output terminal of the transmission line is opposite in phase to a signal at its input terminal. In the adjustment of the delay time, the input and output terminals are short-circuited by a line having a predetermined delay time to form a loop, causing oscillation. The sum of the rise and fall delay times of this loop-like transmission line is the oscillation cycle. Since the rise delay time and the fall delay time are substantially equal to each other over the entire loop, the delay time of the loop-like transmission line is obtained as 1/2 of the reciprocal of the oscillation frequency (the oscillation cycle), and from the delay time thus obtained is subtracted the delay time of the short-circuiting line to obtain the delay time between the input and output terminals of the clock signal distributing circuit. The abovesaid frequency is measured by means of a frequency counter. The delay time is adjusted, for example, by changing the length of a discrete wire.

REFERENCES:
patent: 3505593 (1970-04-01), Gram et al.
patent: 3792362 (1974-02-01), Grant
patent: 4165490 (1979-08-01), Howe, Jr. et al.
patent: 4197506 (1980-04-01), Fogelstrom

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