Clock signal decoupling for synchronous operation

Details Clock signal decoupling for synchronous operation Clock signal decoupling for synchronous operation

2006-05-09

2006-05-09

Kizou, Hassan (Department: 2662)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C370S516000, C370S518000

Reexamination Certificate

active

07042910

ABSTRACT:
Method and apparatus is described for decoupling data from a clock signal and recoupling the data to a different clock signal for subsequent synchronous processing by a pointer processor. More particularly, on a receive or drop side, one buffer is configured to store payload pointers and a synchronous payload envelope arriving clocked by a line clock signal, while another buffer is configure to store TOH or SOH arriving clocked by the line clock signal. Each buffer clocks out such stored information off of a same system clock signal, such as a drop clock signal. On a transmit or add side, a buffer is configured to store payload pointers and a synchronous payload envelope. This buffer clocks in such stored information off of a system clock signal, such as an add clock signal, and clocks out such stored information off of a transmit reference clock signal. Output of such buffers, whether on a drop or add side, is provided to a pointer processor buffer, where both an input side and an output side of the pointer processor buffer are operated off of a system clock signal or a signal synchronized with the system clock signal.

REFERENCES:
patent: 5210762 (1993-05-01), Weeber et al.
patent: 5465252 (1995-11-01), Muller
patent: 5535219 (1996-07-01), Freitas
patent: 5717693 (1998-02-01), Baydar et al.
patent: 5809032 (1998-09-01), Weeber et al.
patent: 5898887 (1999-04-01), Hansen
patent: 5907682 (1999-05-01), Miyazawa
patent: 5923653 (1999-07-01), Denton
patent: 6188685 (2001-02-01), Wolf et al.
patent: 6314097 (2001-11-01), Ohara
patent: 6526069 (2003-02-01), Wolf et al.
patent: 6693918 (2004-02-01), Dallabetta et al.
patent: 6697386 (2004-02-01), Sugawara et al.
patent: 6765928 (2004-07-01), Sethuram et al.
patent: 2003/0031204 (2003-02-01), Ho et al.
patent: 2004/0174870 (2004-09-01), Viks et al.
patent: 0 705 050 (1996-04-01), None
patent: WO 96/41435 (1996-12-01), None
patent: WO 02/095999 (2002-11-01), None
Fuqiang, S. et al., “A SDH STM-N Processor for Overhead Terminating and PDH Interface,” High Technology Letters, vol. 5, No. 1, pp. 25-28, Jun. 1999.
Hamlin, R. et al., “A SONET/SDH Overhead Terminator for STS-3, STS-3C, and STM-1,” IEEE Journal of Solid-State Circuits, vol. 28, No. 3, pp. 276-281, Mar. 28, 1993.
European Patent Office, International Search Report for International Appl. No. PCT/CA01/01105, 9 pages, Nov. 26, 2002.
European Patent Office, International Preliminary Examination Report for International Appl. No. PCT/CA01/01105, 8 pages, Sep. 5, 2003.
U.S. Appl. No. 10/954,947, filed Sep. 29, 2004, Ho et al.
“International Search Report and Written Opinion of the International Searching Authority; Dated Jan. 17, 2006; PCT/US2005/035378”, (Jan. 17, 2006), 12 pgs.

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