Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Reexamination Certificate
2000-06-26
2002-01-22
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Clock or pulse waveform generating
Reexamination Certificate
active
06340910
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a clock signal control circuit, a clock signal control method and a data transmission apparatus employing the control circuit and method. More Particularly, it relates to a phase error averaging circuit for pulse signals suited for clock control of an interface used in high-speed communication and to a data transmission apparatus employing the phase error averaging circuit.
BACKGROUND OF THE INVENTION
Up to now, distribution of multi-phase clocks of two or more phases is by relaying and amplifying respective phase components by a circuit arrangement shown in
FIG. 17
a
. Although not shown, complementary signals (two-phase signals) are occasionally distributed by a relay circuit adapted to cause interaction between the complementary signals. However, the clocks that can be handled by this known device are of two phases at most. Thus, should phase errors td occur as in input signals P
0
to P
7
as may be seen in the timing chart of
FIG. 17
b
, an input clock is amplified with a phase error, as in the cases of Q
2
, or a new phase error is added to the clock, as in the case of Q
5
.
FIG. 18
shows an example of a digital PLL circuit for generating multi-phase or multiplied clocks. In this prior-art example, first to fourth delay circuits
901
to
904
are connected in series by first to fourth switches
905
to
908
. After inputting the first clock
911
, second to fifth clocks
912
to
915
are output. The fifth clock
915
is compared to the first clock
911
by a phase comparator
909
. Based on an UP signal
916
or a DOWN signal
917
, produced by a phase difference, a counter
910
outputs a control signal
918
, which then controls the first to fourth switches
905
to
908
so that the first clock
911
and the fifth clock
915
will be close in phase to each other. This generates first to fourth clocks which are equally spaced apart four-phase clocks. In the case of multiplied clocks, the multiplied clocks are generated using these multi-phase clocks.
Although not shown in the drawings, such a system is also known in which plural delay circuits are arrayed in a ring and control is made of the number of ring steps and the number of cycling times. In this digital PLL circuit, phase errors of the multi-phase clocks produced by quantization errors of the control delay units as well as changes in the period of the multiplied clocks caused by phase errors of the multi-phase clocks are distributed straightly.
Thus, in distributing the multi-phase clocks, since there lacks the interaction between relay amplification circuits for the respective clocks, an increasing distance of distribution of the multi-phase clock signals due to the increased number of the relay amplification circuits leads to gradual increase in the error between the phases due to variations in the delay time of each relay amplification circuit, as a result of which the distributed distance of the multi-phase clocks is limited to the range of allowance of the phase errors.
FIG. 19
shows an example of application of actually distributing the multi-phase clocks. A reception circuit
1001
of
FIG. 19
is such a circuit in which, for producing recovery clocks
1005
synchronized with bits of reception data
1002
as disclosed in JP Patent Kokai JP-10-190642A, a clock selection circuit
1003
selects multi-phase clocks P
O
to P
n
, using transition points of the reception data
1001
, and produces latch data
1006
using recovery clocks
1005
. It is noted that the number of phases of the clocks is arbitrary and n is an integer. This reception circuit usually resides in the combination of a PLL (phase-locked loop) for generating multi-phase clocks P
O
to P
n
and a plurality of reception circuits
1009
-O to
1009
-m, as shown in FIG.
20
. In this case, the multi-phase clocks P
O
to P
n
need to be routed through the reception circuits
1009
-O to
1009
-m. In addition, during such routing, the phase-to-phase phase difference of the multi-phase clocks needs to be kept.
FIGS. 21 and 22
show an arrangement in which reception data are captured by respective latch circuits with respective phases of the multi-phase clocks and processed in the LSI as parallel data. For outputting, the parallel data are again sequentially output as serial data.
This circuit system is disclosed in “A 1.0625 Gb/s Transceiver with 2X oversampling and Transmit Signal Pre-Emphasis” in ISSCC (International Solid-State Circuits Conference), 1997, pages 238 to 239. In the present system, eight-phase clocks P
0
to P
7
as multi-phase clocks are generated in the PLL
1102
on the receiving side, from reference clocks
1101
, as shown in the block diagrams of
FIG. 21
(
a
) and in a timing chart of
FIG. 21
(
b
). Although the eight-phase clocks are used here, the number of phases may be changed depending on the overall circuit structure. The generated eight-phase clocks are routed to a reception circuit
1003
where input data are latched through a phase adjustment circuit
1104
by respective F/F (flip-flops). Since the frequency rate of input data is four times the frequency of each of the eight-phase clocks, the respective phases latch different values depending on changes in data. A phase comparator
1105
detects the data phase from changing points of the latched data to output a control signal
1106
which then is used in a Phase adjustment circuit
1104
so that the edges of the multi-phase clocks will be coincident with those of the data. Since one-half of data latched with the eight-phase clocks is used for detecting an optional phase change point, data detected at four phases, corresponding to every second phases, are output as parallel data.
As may be seen from the timing chart, if the input data assumes values of from D
0
to D
7
per period, the input data are serial/parallel converted every four bits. Also, as may be seen from the block diagram of
FIG. 22
(
a
) and the timing chart of
FIG. 22
(
b
), four-phase clocks of from P
0
to P
3
, as multi-phase clocks, are generated on the transmitting side at the PLL
1202
from the reference clocks
1201
. The generated four-phase clocks are routed to a transmission circuit
1203
where four parallel data are sequentially output as serial data by four parallel gates adapted to be turned on every one-fourth period.
It is seen from the timing chart that the four parallel data DQ
0
to DQ
7
are converted into output serial data DS
0
to DS
7
.
In this system, since the phase components of the multi-phase clocks provide data period components, extremely stringent constraint is placed on the phase-interval errors. So, the transmission circuits and the multi-phase clock generating circuits are used frequently at a ratio of 1:1, that is one transmission circuit is used for one multi-phase clock generating circuit.
SUMMARY OF THE DISCLOSURE
It is an object of the present invention to overcome the deficiencies of the above-mentioned prior art and to provide a novel clock signal control circuit in which it is possible to average phase errors of the respective clock signals as the phase difference between clock signals is maintained. It is another object of the present invention to provide a data transmission apparatus employing this clock signal control circuit.
For accomplishing the above objects, the present invention provides a technical configuration which is basically as defined hereinbelow.
The present invention provides a clock signal control circuit, as its first aspect, wherein multi-phase clock signals are caused to interact to average out respective phase error components of the clock signals as the phases of the respective clock signals are kept.
The present invention provides a clock signal control circuit, as its second aspect comprising a plurality of averaging circuits. Each of averaging circuits causes multi-phase clock signals to interact to average out respective phase error components of the clock signals as the phases of the respective clock signals are kept. The averaging circuits are grouped into a plurality
Hutchins, Wheeler & Dittmar
Nu Ton My-Trang
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