Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Delay controlled switch
Reexamination Certificate
2000-07-20
2001-08-14
Nu ton, My-Trang (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Delay controlled switch
C327S277000, C327S399000
Reexamination Certificate
active
06275091
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a clock signal control circuit and method, and more particularly to a clock signal control circuit that is suited best to be used as a synchronous delay circuit.
BACKGROUND OF THE INVENTION
A circuit for changing the direction in which a clock signal is traveling is known in the prior art. For example, document (1) (IEICE Trans. Electron., Vol. E79-C, No. 6, June 1996, pp798-803) discloses the arrangement of such circuit that is shown in FIG.
3
.
Referring to
FIG. 3
, the circuit includes two groups of individual clocked inverters
31
wherein the first group of individual clocked inverters is connected to allow a clock signal to travel in the forward direction, and the second group of individual clocked inverters is connected to allow the clock signal to travel in the backward direction, with each respective node of the adjacent clocked inverters in the first group being coupled with each respective corresponding node of the adjacent clocked inverters in the second group. When the clock signal travels in the forward direction from a terminal FIN toward a terminal FOUT, the forward clocked inverter sequence
30
A may be enabled by setting a control signal D to High level and by setting a complementary (inversed) signal DB for the control signal to Low level, thereby causing each individual clocked inverters in the backward clocked inverter sequence
30
B to be placed in Hi-Z state (floating state). When the clock signal travels in the backward direction from a terminal BIN to a terminal BOUT, on the other hand, the backward clocked inverter sequence
30
B may be enabled by setting the control signal D to Low level and by setting the complementary signal DB to High level, thereby causing each individual clocked inverter in the forward inverter sequence
30
A to be placed in Hi-Z state.
It may be understood from the above document that each of the forward clocked inverters includes P-type channel MOS transistors (PM
31
to PM
34
), inverters INV
31
to INV
34
and N-type channel MOS transistors NM
31
to NM
34
, respectively, each of which is connected in series between power supply VCC and ground GND. The control signal D may be applied to the gate of each of N-type channel MOS transistors NM
31
to NM
34
, and a signal that may be obtained by inversing the control signal D at the inverter INV
39
may be applied to the gate of each of P-type channel MOS transistors PM
31
to PM
34
. For the backward clocked inverter sequence, each clocked inverter includes P-type channel MOS transistors PM
35
to PM
38
, inverters INV
35
to INV
38
and N-type channel MOS transistors NM
35
to NM
38
, respectively, each of which is connected in series between power supply VCC and ground GND, respectively. The control signal DB may be applied to the gate of each N-type channel MOS transistor NM
35
to NM
38
, and a signal that may be obtained by reversing the control signal DB at the inverter INV
39
may be applied to the gate of each P-type channel MOS transistor PM
35
to PM
38
. The input node and output node of each clocked inverter in the forward clocked inverter sequence is connected to the output node and input node of each corresponding clocked inverter in the backward clocked inverter sequence, respectively.
FIG. 4
shows a typical synchronous delay circuit that incorporates two equivalent delay circuits shown in FIG.
3
and described above. Specifically, this synchronous delay circuit includes a first delay circuit
48
and a second delay circuit
49
, both of which are identical to that shown in FIG.
3
. Each of the first and second delay circuits includes forward and backward clocked inverter sequences (
48
A,
48
B;
49
A,
49
B), respectively, and may be operated under control of the control signal to switch the direction in which the clock signal travels between forward and backward. The synchronous delay circuit further includes an input buffer
47
that may receive input clock
41
, a third delay circuit
43
that may receive an output of the input buffer
47
as input and provide a delayed output that may be fed to an input terminal of each individual clocked inverter in the forward clocked inverter sequences
48
A,
49
A within the first and second delay circuits
48
,
49
, respectively, a frequency divider
45
that may accept the output of the input buffer
47
and provide a frequency-divided output, NAND gate
46
to which the output of each of the clocked inverters in the backward clocked inverter sequences
48
B,
49
B within the first and second delay circuits
48
,
49
may be applied, and a clock buffer
44
that may receive an output of NAND gate
46
.
The output signal from the frequency divider
45
, whose frequency is equal to half the frequency of the input clock, and the output signal of the inverter
40
, which is equivalent to the inversed version of the output signal of the frequency divider, may be used as control signals D and DB, respectively, that cause the individual clocked inverters in the forward and backward clocked inverter sequences
48
A,
48
B within the first delay circuit
48
to be switched on and off, respectively. In addition, the signal that may be obtained by enabling the inverter
40
to reverse the output signal of the frequency divider
45
, having a frequency equal to half the frequency of the input clock, and the signal of the frequency divider
45
that is equal to half the frequency of the input clock may be used as control signals DB and D, respectively. Thus, when the control signal D is at High level, the clocked inverters in the forward clocked inverter sequence
48
A within the first delay circuit
48
and the clocked inverters in the backward clocked inverter sequence
49
B within the second delay circuit
49
may be switched on. When the control signal D is at Low level, the individual clocked inverters in the backward clocked inverter sequence
48
B within the first delay circuit
48
and the individual clocked inverters in the forward clocked inverter sequence
49
A within the second delay circuit
49
may be switched on. In this way, the direction in which the clock signal is traveling through the first and second delay circuits
48
,
49
, respectively, may be switched over alternately between forward and backward at every cycle of the input clock signal.
As this time, the clock signal may be delayed by a predetermined delay time T by the delay circuit
43
before it passes through the respective delay circuits
48
,
49
.
FIG. 5
is a timing diagram that may be used in explaining the operation of the synchronous delay circuit of FIG.
4
. As shown in
FIG. 5
, the clock signal that travels in opposite directions through the first and second delay circuits
48
,
49
, respectively, has a delay time that occurs earlier by a delay time T of the delay circuit
43
, with respect to the sum of a delay time d
1
of the input buffer
47
and a delay time d
2
of a clock buffer
44
, i.e., d
1
+d
2
.
More specifically, the input clock may be delayed by the delay time of d
1
by the input buffer
47
(see FIG.
5
(
b
)), and may further be delayed by the time T by the delay circuit
43
(see FIG.
5
(
c
)). Thus, when the control signal D is at High level, the control signal D that is traveling through the first forward clocked inverter sequence
48
A within the first delay circuit
48
will advance up to the point (timing of tCK−T) where the clock signal D changes to Low level, and at this advance point (timing), it is transferred to the backward clocked inverter sequence
48
B within the first delay circuit
48
. Then, the clock signal D travels through the backward clocked inverter sequence
48
B within the delay circuit
48
, advancing by a time length of tCK−T where an output may be provided at the output terminal (see BOUT in FIG.
3
). Thus, the output of the first delay circuit
48
may be delayed by the delay of tCK−T with regard to the falling edge of the control signal D (see FIG.
5
(
f
), where tN=T). The output of the second d
NEC Corporation
Nu Ton My-Trang
Young & Thompson
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