Clock signal conditioning circuit

Details Clock signal conditioning circuit Clock signal conditioning circuit

1993-12-20

1995-05-23

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

327100, 327 58, 327227, H03K 3017

Patent

active

054184851

ABSTRACT:
A clock signal conditioning circuit (100) for use in a smart card (102) has an input node (112) for receiving an applied clock signal, an output node (126) for producing a conditioned clock signal, a rising/falling edge detector (118) for detecting edges in the received clock signal, a bistable device (122) for forming at the output node a clock signal in response to the edge detector, and a timer (120, 124) for inhibiting switching of the bistable device for a predetermined time (T) following detection by the edge detector of an edge. Such a clock signal conditioning circuit provides a conditioned clock signal which is substantially independent of variations in the duty cycle of the applied clock signal and is substantially immune to glitches in the applied clock signal.

REFERENCES:
patent: 3693028 (1972-09-01), Fussell
patent: 3921081 (1975-11-01), Lane
patent: 3942042 (1976-03-01), Nikami
patent: 3965431 (1976-06-01), Johnson
patent: 4588905 (1986-05-01), Kojima
patent: 4606053 (1986-08-01), Schroder
patent: 4635280 (1987-01-01), Smith et al.
patent: 4937468 (1990-06-01), Shekhawat et al.
patent: 5003196 (1991-03-01), Kawaguchi

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