Clock signal cleaning circuit

Details Clock signal cleaning circuit Clock signal cleaning circuit

1998-11-20

2001-06-12

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S166000, C327S018000, C327S023000, C327S034000, C375S371000

Reexamination Certificate

active

06246276

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to jitter removing circuits, clock averagers and other clock signal correction devices.
2. Description of Related Art
At present jitter is controlled by prevention rather than cure. By the use of good design technique the effects of factors such as current surges, temperature, EM interference etc, are minimised. However there are many instances where despite such measures jitter is introduced into the system via transmission, mechanical devices and the like. Clock recovery systems, which recover clock signals distorted by transmission usually incorporate a high quality crystal which is used as a reference and as a source if a clock pulse is missing.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an improved clock signal cleaning circuit. Presented is a device which removes jitter from a clock signal. The device is based upon a basic unit which is repeated throughout the device. The behaviour of this basic unit determines its jitter removal capabilities.
In its present embodiment the invention can be considered passive, however it is possible to include feedback loops connected to the oscillator to compensate for environmental conditions including aging.
The basic unit comprises a number of delay elements connected in series. The output of each delay is connected to the input of a multi-input AND gate. The output from the basic unit exhibits a narrower spectrum than the original spectrum. This statement must be qualified in that the actual signal emerges with an uneven duty cycle. By feeding the output from any of the basic units to a flip-flop a clock signal of half the original frequency is created with a 50% duty cycle because the times between positive to negative transitions is constant. After being passed through a frequency doubler the resulting spectrum of this signal is narrower than the original.
In an embodiment of the present invention a ‘front end’ includes a circuit which compensates for missing pulses. Conveniently, any number of basic units can be connected in series. Each of their outputs are fed into a respective flip-flop and to a respective AND gate. There are one less AND gates connected such that the output from only one basic unit is let through to an EXOR gate. The output from there is presented to various basic units of different size, all connected in series.
The output from there is fed to a flip-flop which corrects the uneven duty cycle but produces a signal whose frequency is half that input. Either this signal can be used, or the signal can be applied to a frequency doubler to create a clock signal at the original frequency.
A further embodiment of the present invention is directed to an electronic circuit for the reduction of jitter and temporary frequency drifts of a fixed oscillating source comprising:
an input, an output, a plurality of delay elements serially connected between the input and the output; and
an NAND/AND gate having a plurality of inputs and an inverting and non-inverting output, each of said plurality of inputs of said NAND/AND gate being connected to a respective output of said plurality of delay elements;
said electronic circuit comprising a basic unit.
Other embodiments of this invention include the electronic circuit as described above along with a duty cycle recovery module, or a module that includes an edge triggered flip flop. This invention also relates to the electronic circuit as described above comprising a frequency doubler coupled to the output of the edge trigger flip flop.
Another embodiment of this invention includes the electronic circuit as defined above which comprises a missing clock pulse detection and substitution module which is coupled to the input of the electronic circuit.
Furthermore, this invention relates to a method for reducing jitter and temporary frequency drifts of a fixed oscillating source comprising the steps of successively delaying a jittery source signal to generate a plurality of delayed signals, and gating the plurality of delayed signals together to derive a clean signal.
Furthermore, this invention relates to this method further comprising successively delaying the cleaned signal to provide a plurality of delayed clean signals, detecting a missing pulse in one of the plurality of delayed clean signals, and substituting therefore another pulse and one of the plurality delayed clean clock signals, and outputting a single clean signal without a missing pulse.
This invention is also directed to the above comprising the deriving from a single clean signal, a third clock signal having a 50% duty cycle and a frequency of ½ that of the single clean cycle. This invention also encompasses the above method wherein the third signal is doubled to generate a fourth signal having a frequency equal to that of the single clean signal.


REFERENCES:
patent: 3599103 (1971-08-01), Nussbaumer
patent: 4649438 (1987-03-01), Shimizu et al.
patent: 4805197 (1989-02-01), Van Der Jagt et al.
patent: 5349612 (1994-09-01), Guo et al.
patent: 0476968 A2 (1992-03-01), None
patent: 0576150 A2 (1993-12-01), None

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