Clock signal and line voltage control for efficient power consum

Details Clock signal and line voltage control for efficient power consum Clock signal and line voltage control for efficient power consum

1995-05-18

1998-03-10

Butler, Dennis M.

39575001, G06F 108

Patent

active

057271933

ABSTRACT:
A frequency of an operation clock signal CPCK output from a PLL circuit 3 is determined with division factors N and M stored in division factor memories 2 and 12. A voltage control signal LPS is input into a voltage-controlled oscillator in the PLL circuit 3 as well as to a line voltage control circuit 9. The line voltage control circuit 9 controls the level of a line voltage E supplied to other circuits including a CPU 1, in response to the voltage control signal LPS. Efficient power consumption and an appropriate operation speed are simultaneously attained because both of the frequency of the operation clock signal CPCK and the level of the line voltage E depend upon the voltage level of the voltage control signal LPS.

REFERENCES:
patent: 4405898 (1983-09-01), Flemming
patent: 4700124 (1987-10-01), Anderson
patent: 4766567 (1988-08-01), Kato
patent: 4893271 (1990-01-01), Davis et al.
patent: 5367638 (1994-11-01), Niessen et al.
patent: 5469561 (1995-11-01), Takeda
patent: 5526253 (1996-06-01), Duley
patent: 5526313 (1996-06-01), Etoh et al.

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