Clock signal adjusting method and apparatus

Details Clock signal adjusting method and apparatus Clock signal adjusting method and apparatus

1995-02-23

1998-11-24

Heckler, Thomas M.

395552, G06F 112

Patent

active

058420010

ABSTRACT:
A clock signal adjusting method and apparatus are applicable to an information processing system in which clock signals are distributed from a clock generating unit to a plurality of load units, each of the plurality of load units having at least a load element operated in synchronism with a clock signal input to each of the load units. In the clock signal adjusting method and apparatus, delay times set in each of a plurality of delay units are measured in accordance with setting instructions, each of the plurality of delay units delaying an input signal by a delay time set therein, setting instructions corresponding to delay times to be set in the plurality of delay units are input to the plurality of delay units based on measuring results obtained in the previous step, reference phase signals having predetermined phase differences are generated based on outputs of the plurality of delay units, and a phase of the clock signal distributed for the load element in each of the load units is adjusted based on phases of the reference phase signals thus generated.

REFERENCES:
patent: 4063308 (1977-12-01), Collins et al.
patent: 5204559 (1993-04-01), Deyhimy et al.
patent: 5220660 (1993-06-01), Yoshizawa et al.
patent: 5481563 (1996-01-01), Hamre

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