Clock shaping circuit and electronic equipment

Details Clock shaping circuit and electronic equipment Clock shaping circuit and electronic equipment

2002-11-01

2004-03-09

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C331SDIG002, C375S376000

Reexamination Certificate

active

06703877

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to a clock shaping circuit, which receives a clock signal containing jitters and outputs a clock signal with reduced jittering and, in particular, to a clock shaping circuit having a PLL (Phase Locked Loop).
2. Description of the Related Art
To meet a high data rate, an oscillator in electronic equipment such as a communication apparatus must stably oscillate at a high frequency region (with a high frequency stability) and within a practical temperature range (with a temperature compensation).
Communication apparatuses use a clock signal when transmitting or receiving data. In this case, the clock signal must be free from jitters. To obtain a stable and jitter-free clock signal, a clock shaping circuit
10
incorporating a PLL circuit is used as shown in
FIGS. 17 and 18
.
FIG. 17
is a block diagram generally illustrating a conventional clock shaping circuit.
This clock shaping circuit is widely referred to as a jitter-reducing circuit. The clock shaping circuit is also referred to as a dejittering circuit, a jitter clean-up circuit, or a clock smoothing circuit. A PLL circuit having a voltage-controlled oscillator (a clock generator) is used. In response to a clock signal S
1
input thereto containing jittering, a clock shaping circuit
1
outputs a clock signal S
3
with the jittering thereof reduced.
In the clock shaping circuit, the voltage-controlled oscillator may employ a voltage-controlled SAW (Surface Acoustic Wave) oscillator VCSO using a SAW resonator, or a voltage-controlled liquid-crystal oscillator (VCXO) to improve phase noise and jitter characteristics.
The clock shaping circuit
10
shown in
FIG. 18
includes a phase comparator
3
, a loop filter
2
, a voltage-controlled oscillator VCSO/VCXO
4
, a buffer
9
, and a feedback loop (hereinafter simply referred to as a closed loop) of a PLL circuit.
The phase comparator
3
in the clock shaping circuit
10
thus constructed compares the phase of the clock signal S
1
containing jitters with the phase of the feedback clock signal (hereinafter referred to as a comparison clock signal) S
2
fed back from the VCSO/VCXO
4
, and outputs a control signal responsive to the results of the comparison. The output is then subjected a smoothing process through the loop filter
2
, and is then applied to a voltage control terminal of the VCSO/VCSO
4
, thereby controlling the oscillation of the VCSO/VCSO
4
.
Although the clock signal S
1
contains a jittering component, the buffer
9
outputs a clock signal with the level of jittering thereof lowered because the loop bandwidth of the PLL circuit limits the frequency component of the jitter.
Conventional clock shaping circuits typically employ an LC-VCO, composed of an inductance and a capacitor, used as the VCO
4
, or a ring oscillator. For this reason, the conventional clock shaping circuits suffer from poor phase noise characteristics and poor jitter characteristics, and is unable to reduce jitters.
To improve phase noise and jitter characteristics, one clock shaping circuit employs a voltage-controlled crystal oscillator VCXO or a voltage-controlled SAW oscillator VCSO with a SAW resonator, as a voltage-controlled oscillator VCO shown in FIG.
19
.
The SAW resonator is one which makes use of the property of an elastic body that concentrates and propagates energy near the surface of the body. Interdigital transducers are disposed on a piezoelectric substrate. A surface acoustic wave excited by the transducers are reflected, generating a standing wave. The assembly thus functions as a resonator. The SAW resonator oscillates within a frequency range from several tens of MHz to several hundreds of MHz. In terms of frequency-temperature characteristics and costs, this resonator is less preferable than an AT cut quartz crystal resonator.
Interfacing such as impedance matching in an input/output interface and a transmission line (a wiring line for interconnection in this case) is somewhat difficult in terms of the transfer of a clock signal in the above construction in a high frequency region of several hundreds of MHz. The input and output sides adversely affect each other, thereby lowering an output amplitude level of a signal. In case of a differential output, the amplitudes of output signals between a positive output terminal and a negative output terminal are unbalanced, and a phase difference occurs between the two terminals.
To avoid the problem, a known clock shaping circuit shown in
FIG. 20
includes, as a separate integrated circuit (hereinafter referred to as an IC), an output buffering driver IC (a buffer
9
) attached to the output of a voltage-controlled crystal oscillator VCXO or a voltage-controlled SAW oscillator VCSO. The addition of the output buffering driver IC increases a component count, and a compact design is difficult to implement in the clock shaping circuit.
There are times when, for some reason, the conventional clock shaping circuit suffers from an interruption of the supply of the clock signal S
1
from the outside, a substantial change in the frequency thereof, and an out-of-lock state in the phase and frequency. In such a case, a closed loop enters a free run condition. The clock shaping circuit fails to output a stable clock signal having excellent phase noise and jitter characteristics. If data is transferred based on that clock signal, data transfer malfunctions.
The reasons why the output clock signal loses its stability in the free-run state are that a control signal applied to the VCO
4
is not appropriate, and that the frequency varies due to the temperature characteristics of the VCO
4
. If the VCO
4
is formed of a voltage-controlled oscillator LC-VCO composed of a capacitor and inductance, a ring oscillator, or a voltage-controlled SAW oscillator having a SAW resonator, an inconvenience of frequency variation due to a change in temperature becomes large.
The present invention has been developed to resolve the above problem, and it is an object of the present invention to provide a clock shaping circuit, which does not directly affect a clock signal when the output of the voltage-controlled quartz crystal oscillator VCXO, or the voltage-controlled SAW oscillator VCSO, is used as a feedback loop output., and which is free from an unbalance of an output amplitude and a phase difference in differential outputs between positive and negative output terminals.
It is another object of the present invention to provide a clock shaping circuit, which has a smaller component count with no output buffering driver IC required, and is easy to miniaturize.
It is yet another object of the present invention to provide a clock shaping circuit, which outputs a clock signal with less jitters even when an out-of-lock state occurs for some reason.
It is a further object of the present invention to provide a clock shaping circuit, which includes a voltage-controlled SAW oscillator exhibiting improved frequency-temperature characteristics regardless of a change in temperature.
It is still a further object of the present invention to provide electronic equipment, which continuously operates without interruption with a clock shaping circuit thereof assuring a clock signal containing less jittering even when the clock shaping circuit is unlocked for some reason.
SUMMARY OF THE INVENTION
A clock shaping circuit of a first aspect includes a clock generator, which changes a frequency of an output comparison clock signal in response to a supplied control voltage, a phase comparator, which generates a phase difference signal based on the results of comparison of the comparison clock signal from the clock generator with an input signal from the outside, and a loop filter for smoothing the phase difference signal, wherein the clock generator includes a positive feedback oscillation loop including, at least, a piezoelectric resonator, an oscillation differential amplifier, a feedback buffering differential amplifier, and a voltage-controlled phase shifter for shifting a

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