Clock selection for a communications processor having a...

Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – Having selection between plural continuous waveforms

Reexamination Certificate

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Details

C327S298000

Reexamination Certificate

active

08008949

ABSTRACT:
A clock selector operative on two clocks operating on different domains and responsive to a SELECT input provides a transition from a first clock to a second clock, and from a second clock to a first clock with a dead zone therebetween. The delay is provided by a doublet register having a first register coupled to a second register, the two registers operative on one of the clock domains. Additionally, a clock selector is operative on two clocks which are each accompanied by a clock availability signal where the state machine provides a variety of states to create a dead zone between selections, and to bring the state machine to a known state until a clock signal is again available.

REFERENCES:
patent: 5099141 (1992-03-01), Utsunomiya
patent: 5579350 (1996-11-01), Furukawa et al.
patent: 6563349 (2003-05-01), Menezes et al.
patent: 7427881 (2008-09-01), Starr et al.

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