Clock selection circuit

Details Clock selection circuit Clock selection circuit

1989-12-26

1991-01-01

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307269, 307441, 3072964, H03K 3027, H03K 1704

Patent

active

049821164

ABSTRACT:
A clock selection circuit having a single input terminal for receiving an external clock signal and including logic means for selectively passing an external clock signal and an internal clock signal to an output. A clock detector is connected to the input terminal for generating a voltage in response to an external clock signal. The generated voltage is utilized in controlling the logic circuitry in selectively passing the external clock signal or the internal clock signal. In a preferred embodiment, the logic circuitry includes a first two input NAND gate, a second two input NAND gate, and a third two input NAND gate. One input of the first NAND gate receives the external clock signal, and one input to the second NAND gate receive sthe internal clock. The two outputs of the first and second NAND gates are connected to the inputs of the third NAND gate. The output from the clock detector is connected to the other input of the first NAND gate and is connected through an inverter to the other input of the second NAND gate.

REFERENCES:
patent: 4365174 (1982-12-01), Kucharewski
patent: 4553054 (1985-11-01), Kase et al.
patent: 4886983 (1989-12-01), Taka

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