Clock scan design from sizzle global clock and method therefor

Details Clock scan design from sizzle global clock and method therefor Clock scan design from sizzle global clock and method therefor

1996-05-29

1998-05-05

Nguyen, Hoa T.

Excavating

371 2236, G01R 3128

Patent

active

057486450

ABSTRACT:
A scan based test methodology generates conventional functional clocks (CLK1 and CLK2) and test clocks (CLKA and CLKB) from a single input clock (GCLK). The methodology allows an integrated circuit (10) designed according to it to be tested at the part's operating frequency. Also, the test methodology is compatible with known test methodologies such as level sensitive scan design ("LSSD"). The pre-existing body of test programs and equipment can be used with a circuit incorporating the invention. The single clock requirement also simplifies design.

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