Clock scaling to optimize PLL clock generation accuracy

Details Clock scaling to optimize PLL clock generation accuracy Clock scaling to optimize PLL clock generation accuracy

2007-10-30

2007-10-30

Lee, Benny (Department: 2817)

Oscillators

Combined with particular output coupling network

C331S018000, C331S17700V

Reexamination Certificate

active

11131621

ABSTRACT:
A method and system for scaling a phase lock loop (PLL) based clock, includes: selecting a clock frequency; selecting a reference frequency, multipliers, and an output divider for an output frequency of a PLL, where the output frequency is higher than the clock frequency; applying the multipliers and the output divider to the reference frequency to generate the output frequency, outputted to a programmable logic chip; and applying a counter factor to the output frequency by the programmable logic chip to generate the clock frequency. By scaling the reference frequency in more than one step, the middle ranges of the multipliers are widened, allowing for a greater granularity of control over the increments by which the reference frequency can be adjusted. Smaller frequency errors result. The printer emulator utilizing the present invention has a set of more exactly generated clock frequencies that emulate a variety of printer speeds and resolutions.

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