Clock routing in multiple channel modules and bus systems

Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices

Reexamination Certificate

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Details

C361S777000, C361S775000, C327S323000, C327S332000, C377S078000

Reexamination Certificate

active

07027307

ABSTRACT:
An apparatus is provided, which includes a memory interface circuit, a clock signal generating circuit, and a plurality of memory circuits. The memory circuits are operatively coupled and arranged in an order on a plurality of memory modules, such that the memory module positioned at the beginning of the order is coupled to an output of the clock signal generating circuit and the memory interface circuit. The memory module that is positioned at the end of the order is unique in that it includes a clock signal terminating circuit connected to the last memory integrated circuit. With this configuration, a clock loop is formed by directly routing the clock signal from the output of the clock signal generating circuit through each of the memory modules in the order (without connecting to any of the intervening memory integrated circuits) to the memory integrated circuit positioned at the end of the order. Then, the clock signal is asserted on the previous memory modules by routing it back through the memory integrated circuits thereon, in reverse order to the memory integrated circuit positioned at the beginning of the order and from there to the memory interface circuit. To complete the clock loop, the clock signal is again asserted by routing it from the memory interface circuit back through the memory integrated circuits in order to the memory integrated circuit positioned at the end of the order. Finally, the clock signal is terminated at the clock signal terminating circuit on the memory module positioned at the end of the order.

REFERENCES:
patent: 5224023 (1993-06-01), Smith et al.
patent: 5276817 (1994-01-01), Matschke et al.
patent: 5523703 (1996-06-01), Yamamoto et al.
patent: 5625169 (1997-04-01), Tanaka
patent: 5635761 (1997-06-01), Cao et al.
patent: 5680297 (1997-10-01), Price et al.
patent: 5910151 (1999-06-01), Adedokun
patent: 5910885 (1999-06-01), Gulachenski et al.
patent: 5943573 (1999-08-01), Wen
patent: 5981870 (1999-11-01), Barcley et al.
patent: 6003121 (1999-12-01), Wirt
patent: 6005776 (1999-12-01), Holman et al.
patent: 6142830 (2000-11-01), Loeffler
patent: 6172895 (2001-01-01), Brown et al.
patent: 6243272 (2001-06-01), Zeng et al.
patent: 6392897 (2002-05-01), Nakase et al.
patent: 6404660 (2002-06-01), Gamini et al.
patent: 6765800 (2004-07-01), Haba et al.
patent: 2004/0105240 (2004-06-01), Haba et al.

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