Clock routing design method using a hieraichical layout design

Details Clock routing design method using a hieraichical layout design Clock routing design method using a hieraichical layout design

1997-10-16

1999-03-30

Teska, Kevin J.

Boots, shoes, and leggings

364489, 364490, 364488, G06F 1560

Patent

active

058896821

ABSTRACT:
A clock routing design method enables a routing design for each hierarchy while paying an attention to each layout hierarchy to which a branch of a clock signal system extends and considering a whole chip. In the clock routing design method, a clock signal line is routed between a plurality of receiver terminals over a plurality of layout hierarchies while considering an equal-delay branch point yielding equal delays of a clock signal at the receiver terminals, the clock signal line is then routed between the equal-delay branch point positioning between the plural receiver terminals and the driver terminal. The clock routing design method is applicable to a layout design of wire patterns, cell, etc. on LSIs, printed circuit boards and the like.

REFERENCES:
patent: 5309035 (1994-05-01), Watson, Jr. et al.
patent: 5339253 (1994-08-01), Carrig et al.
patent: 5410491 (1995-04-01), Minami
patent: 5416861 (1995-05-01), Koh et al.
patent: 5583788 (1996-12-01), Kuribayashi

Affiliated with

Also associated with

Rating

Clock routing design method using a hieraichical layout design does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock routing design method using a hieraichical layout design, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock routing design method using a hieraichical layout design will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1220390