Clock ripple reduction in a linear low dropout C/DMOS regulator

Details Clock ripple reduction in a linear low dropout C/DMOS regulator Clock ripple reduction in a linear low dropout C/DMOS regulator

1988-06-08

1989-02-07

Salce, Patrick R.

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

363 60, 307270, G05F 156

Patent

active

048036129

ABSTRACT:
A pair of voltage triplers are formed in a C/DMOS circuit along with a self-isolated DMOS transistor. The voltage triplers are driven in phase opposition from the system clock and their outputs commonly drive the gate of the DMOS transistor which acts as the pass element in a voltage regulator. A control circuit includes a reference voltage generator and a differential amplifier that senses a fraction of the d-c output voltage. The amplifier has an output coupled to the DMOS gate thereby to create a stabilizing negative feedback loop. The voltage triplers overdrive the DMOS transistor so the dropout voltage is low and the full wave rectifier action will double the clock frequency for easier filtering.

REFERENCES:
patent: 4053821 (1977-10-01), Hose, Jr. et al.
patent: 4484092 (1984-11-01), Campbell, Jr.
patent: 4553082 (1985-11-01), Nesler
patent: 4626697 (1986-12-01), Nelson
patent: 4737667 (1988-04-01), Tihanyi

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