Clock reset address decoder for block memory

Details Clock reset address decoder for block memory Clock reset address decoder for block memory

2007-08-28

2007-08-28

Mai, Son L. (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230080, C365S233100

Reexamination Certificate

active

11252094

ABSTRACT:
In one embodiment of the invention, an address decoder for decoding a word-line address to energize a word line in a block of computer memory. Instead of relying on a distinct enable signal, a clock signal provides a reset function and an enable function to the address decoder. In one implementation, the address decoder includes negative-level-sense latches and 3-input AND gates to generate decoded address bits. Using the clock signal as one of the inputs to the AND gates ensures that all of the decoded address bits are 0 when the clock signal is low and that exactly one decoded address bit is 1 when the clock signal is high. In this way, the address decoder ensures that two or more word lines are not energized at the same time.

REFERENCES:
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patent: 5648931 (1997-07-01), Obara
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patent: 6501702 (2002-12-01), Takagiwa et al.
patent: 2001/0048632 (2001-12-01), Takagiwa et al.
patent: 2006/0098520 (2006-05-01), Asano et al.

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