Pulse or digital communications – Synchronizers – Feedback – receiver to transmitter
Reexamination Certificate
1998-11-03
2001-07-24
Chin, Stephen (Department: 2734)
Pulse or digital communications
Synchronizers
Feedback, receiver to transmitter
C375S362000, C375S375000, C370S503000, C370S518000
Reexamination Certificate
active
06266383
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock reproduction circuit and a data transmission apparatus which can be applied to a serial data transmission apparatus etc. for transmitting serial data at a high speed.
2. Description of the Related Art
Serial data transmission enables transmission of signals by one or a pair of transmission media, therefore is excellent in space saving and does not suffer from the problem of skew (timing deviation) between data occurring when transmitting signals by a signal transmission line having many cores, therefore is suited to long distance data transmission.
FIG. 5
shows a configuration of a general serial data transmission apparatus. The illustrated data transmission apparatus is constituted by a transmission unit
10
, a transmission line
20
, and a reception unit
30
. Further, the transmission unit
10
comprises a parallel/serial conversion circuit
11
and a transmission clock generation circuit
12
, while the reception unit
30
comprises a serial/parallel conversion circuit
31
and a clock reproduction circuit
32
.
Further, the transmission line
20
is constituted by a pair of signal lines, for example, a shielded twisted pair (STP) or unshielded twisted pair (UTP).
At the time of data transmission, for example, n bits of transmission data input to the transmission unit
10
are converted to serial data in synchronization with a transmission clock signal TCK by the parallel/serial conversion circuit
11
and then output to the transmission line
20
.
The transmission clock generation circuit
12
is constituted by for example a PLL circuit, receives a synchronization clock signal CLK, generates a transmission clock signal TCK in accordance with this, and outputs the same to the parallel/serial conversion circuit
11
.
The reception unit
30
receives the serial data transmitted through the transmission line
20
, converts this to n bits of data by the serial/parallel conversion circuit
31
, and then output the same.
The clock reproduction circuit
32
is constituted by for example a PLL circuit, reproduces a reception use clock signal LCK having the same frequency as that of the transmission clock signal TCK based on the transmission data of the transmission line
20
, and supplies the same to the serial/parallel conversion circuit.
By the above data transmission apparatus, the transmission data can be transmitted at a high speed by for example a pair of transmission lines, so there is excellent space saving of transmission line. Further, data transmission over a long distance with little distortion of data can be realized.
The data transmission apparatus of the above-mentioned related art has the problem that a circuit for extracting the clock signal from the transmission data per se, that is, the clock reproduction circuit
32
, is indispensable for the reception unit
30
to correctly receive the data transmitted from the transmission unit
10
.
The clock reproduction circuit
32
can be constituted by a band pass filter having a high Q value or a PLL circuit.
When the clock reproduction circuit
32
is constituted by a band pass filter, generally the differential waveform of the received signal is filtered by a surface acoustic wave (SAW) filter or the like to extract the clock signal. In this method, there is the limitation that this cannot be applied to a transmission rate other than the center frequency of the SAW filter.
When the clock reproduction circuit
32
is constituted by the PLL circuit, control is performed so that the phase of the received signal and the phase of the output of a voltage-controlled oscillator (VCO) become equal and the clock signal is extracted. In this method, there is an advantage that it is possible to handle a variety of data transmission rates if a wide oscillation frequency range of the VCO is taken.
However, when the frequency of the VCO deviates by a large extent from the frequency of the received signal, a phase comparing means, which assumes serial data signals of a random bit train, becomes confused, the VCO drifts in state or becomes locked to a frequency of a whole multiple of the transmission rate, and the transmission clock signal TCK sometimes cannot be correctly extracted.
One method of solving the above problem, is adopted of applying a reference clock signal having a frequency of a specific ratio relative to the rate of the signal to be transmitted to the reception unit
30
and locking the PLL circuit in an initialized state of the reception unit
30
. Using this method, however, when the transmission rate of the serial data transmitted by the transmitter is not known, the frequency of the reference clock signal cannot be set, therefore another means of transmitting information concerning the transmission rate becomes necessary.
SUMMARY OF THE INVENTION
The present invention was made in consideration with such a circumstance and has as an object thereof to provide a clock reproduction circuit capable of properly reproducing a clock with a simple circuit structure and a data transmission apparatus which can handle a wide range of transfer rates, has a reproduced clock signal which can quickly track the transmission clock, and does not need to increase the transmission media.
To achieve the above object, according to a first aspect of the present invention, there is provided a clock reproduction circuit comprising a clock generation circuit for generating a clock signal based on input data in synchronization with a basic clock when a switch signal is not input and generating a clock signal locked to the frequency of a reference clock signal based on the reference clock signal generated based on the basic clock when a switch signal is input and an error detection circuit for defining a difference of input data sampled at a plurality of points having different phases of the clock signal generated at the clock generation circuit as the error, detecting whether the error is a chance error or an error due to a deviation of the frequency between the generated clock signal and the input data, and outputting a switch signal to the clock generation circuit in the case of a frequency deviation error.
Further, in the present invention, the clock generation circuit comprises a phase comparison circuit actuated and comparing phases of the generated clock signal and the input data when a switch signal is not input; a frequency comparison circuit actuated and comparing frequencies of the generated clock signal and the reference clock signal when a switch signal is input; and an oscillation controlled circuit oscillating at an oscillation frequency in accordance with a result of comparison of the phase comparison circuit and the frequency comparison circuit to generate the clock signal and outputting the same to the phase comparison circuit, frequency comparison circuit, and error detection circuit.
Further, in the present invention, the error detection circuit comprises an error pulse signal generation circuit for outputting a difference of input data sampled at a plurality of points having different phases of the clock signal generated at the clock generation circuit as an error pulse signal; a first circuit for stretching a pulse width of the error pulse signal by exactly a first time and checking a density of the error; and a second circuit for further stretching a pulse width of the output signal of the first circuit by exactly a second time and outputting a switch signal when there is still a part having a high error density after the stretching by the second time.
Further, in the present invention, the error detection circuit comprises a third circuit for suppressing the output of the switch signal even if there is still a part having the high error density even after stretching the pulse for the second time until the phase of the clock signal is pulled to the phase of the input data when the switch signal is output, the frequency of the clock signal is pulled to the frequency of the reference clock signal to stop the output of the swi
Chin Stephen
Ha Dac V.
Kananen Ronald P.
Rader Fishman & Grauer
Sony Corporation
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