Clock reproduction circuit

Details Clock reproduction circuit Clock reproduction circuit

2008-03-11

2008-03-11

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

C327S291000, C375S286000, C375S287000, C375S294000

Reexamination Certificate

active

11392041

ABSTRACT:
A clock reproduction circuit receives a multi-valued input data signal to generate a reproduced clock signal with a higher accuracy. The clock reproduction circuit includes a data judgement block which judges whether or not three consecutive data are such that a first-order data is equal to a third-order data and is not equal to a second-order data, and a phase-locked-loop (PLL) which controls or does not control the phase of the reproduced clock depending on the judgement result by the data judgement block.

REFERENCES:
patent: 7099400 (2006-08-01), Yang et al.
patent: 05-236043 (1993-09-01), None

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