Clock reproduction circuit

Details Clock reproduction circuit Clock reproduction circuit

2005-03-01

2005-03-01

Wambach, Margaret R. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Counter controlled counter

C327S151000, C327S160000, C327S153000, C327S161000, C327S162000, C327S299000

Reexamination Certificate

active

06862332

ABSTRACT:
A master clock signal source (10) generates a master clock signal having a frequency equal to N times the bit rate of received data, where N is a positive integer. A modulo-N counter (12) counts the master clock signal. An edge detecting circuit (4) detects a transition of the received data from a H level to a L level. A counter (8) counts the master clock signal and resets the modulo-N counter (12) if the count counted during a time period in which three edge representative signals occur is 2N. In accordance with the count in the modulo-N counter12, a clock generating unit14generates a clock signal.

REFERENCES:
patent: 4841167 (1989-06-01), Saegusa
patent: 60-224346 (1985-11-01), None
patent: 02-050643 (1990-02-01), None
patent: 08-331189 (1996-12-01), None
patent: 10-313301 (1998-11-01), None
patent: 11-068728 (1999-03-01), None

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