Clock reproduction and identification apparatus

Details Clock reproduction and identification apparatus Clock reproduction and identification apparatus

1999-08-18

2001-06-19

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Regenerating or restoring rectangular or pulse waveform

C327S166000, C327S156000

Reexamination Certificate

active

06249160

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a clock reproduction and identification apparatus for reproducing an identification clock from a data signal and identifying input data.
2. Description of the Related Art
FIG. 14
shows a clock reproduction and identification apparatus in a related art shown in “Proceedings of Electronics Society Conference of IEICE”, C-12-44 in 1998, for example.
The configuration and operation of the clock reproduction and identification apparatus in the related art will be discussed.
Here, phase synchronization means
1
is made up of a phase comparison circuit
2
, an integration circuit
3
, and a voltage-controlled oscillation circuit (VCO). The phase comparison circuit
2
is a logic circuit having a phase comparison characteristic as shown in FIG.
15
. That is, assuming that the transmission line clock cycle is
2
&pgr;, when the phase difference between input data and an identification clock output by the VCO 4, &phgr;, is −&pgr;<&phgr;<0, logic high is output; when the phase difference &phgr;is 0<&phgr;<&pgr;, logic low is output.
When &phgr;=0, a mid-point potential of logic high and logic low is output. The integration circuit
3
is a low-pass filter having a sufficiently long time constant relative to the transmission line clock cycle. Further, the VCO
4
has a control voltage vs oscillation frequency characteristic as shown in FIG.
16
.
FIG. 17A
is a timing chart applied when the identification clock phase leads. The phase comparison circuit
2
compares an input data change point with the falling timing of the identification clock and outputs logic high. The integration circuit
3
integrates output of the phase comparison circuit
2
with a sufficiently large time constant relative to the transmission line clock cycle, and output gradually makes a transition to logic high. Output of the integration circuit
3
is input as control voltage of the VCO
4
, and oscillation frequency decreases. Therefore, the phase difference &phgr; decreases in the direction in which the input data change point matches the falling timing of the identification clock.
FIG. 17B
is a timing chart applied when the identification clock phase lags. The phase comparison circuit
2
outputs logic low and output of the integration circuit
3
gradually makes a transition to logic low. The oscillation frequency of the VCO
4
increases, and the phase difference &phgr; decreases in the direction in which the input data change point matches the falling timing of the identification clock.
FIG. 17C
is a timing chart in a synchronization state in which the input data signal change point matches the falling timing of the identification clock. The phase comparison circuit
2
outputs a mid-point potential of logic high and logic low and the integration circuit
3
also outputs a mid-point potential of logic high and logic low. The oscillation frequency of the VCO
4
is fixed, and the synchronization state in which the input data change point matches the falling timing of the identification clock is maintained. Assuming that the phase comparison circuit
2
has an infinite gain in the synchronization state, output becomes undefined between logic high and logic low because of jitter contained in the input data signal and the identification clock. However, in optical communication apparatuss, etc., generally the data signal is scrambled and the mark rate is 0.5, thus output of the integration circuit
3
becomes a mid-point potential of logic high and logic low.
Thus, the phase synchronization means
1
converges on the synchronization state in which the input data change point matches the falling timing of the identification clock. Identification means
5
can identify and reproduce the data signal in the optimum identification phase for input data by identifying the input data on the rising edge of the identification clock.
The operation of the phase synchronization means
1
has been described with reference to
FIGS. 17A
to
17
C by assuming that the duty of input data is 100% (the duty means the time percentage from the rising edge to the falling edge to the transmission line clock cycle) In fact, however, the duty of input data may change due to waveform distortion of an equalization amplifier, etc., connected to the preceding stage.
FIGS. 18A
to
18
C are timing charts of the phase synchronization means
1
applied when input data contains distortion. In the description to follow, assume that input data contains distortion such that the logical high time becomes longer than the logical low time.
FIG. 18A
is a timing chart applied when the rising edge of input data matches the falling phase of the identification clock. At the rising change point of the input data, the rising edge of input data matches the falling edge of the identification clock in phase, thus the phase comparison circuit
2
outputs a mid-point potential. At the falling change point of the input data, the falling phase of the identification clock leads, thus the phase comparison circuit
2
outputs logic high. Output of integration circuit
3
makes a transition to logic high and the oscillation frequency of the VCO
4
decreases. Therefore, the phase difference &phgr; shifts in the direction in which the falling change point of the input data matches the falling timing of the identification clock.
FIG. 18B
is a timing chart applied when the falling edge of input data matches the falling phase of the identification clock. At the rising change point of the input data, the falling phase of the identification clock lags, thus the phase comparison circuit
2
outputs logical low. At the falling change point of the input data, the falling edge of the input data matches the falling edge of the identification clock in phase, thus the phase comparison circuit
2
outputs a mid-point potential. Output of integration circuit
3
makes a transition to logic low and the oscillation frequency of the VCO
4
increases. Therefore, the phase difference &phgr; shifts in the direction in which the rising change point of the input data matches the falling timing of the identification clock.
FIG. 18C
is a timing chart applied when the center of input data matches the rising phase of the identification clock. The phase is an intermediate phase state of the phases shown in FIGS. A and B. At the rising change point of the input data, the falling phase of the identification clock lags, thus the phase comparison circuit
2
outputs logical low.
At the falling change point of the input data, the falling phase of the identification clock leads, thus the phase comparison circuit
2
outputs logic high. Since distortion of the input data is that the logical high time is longer than the logical low time, output of integration circuit
3
makes a transition to logic low and the oscillation frequency of the VCO
4
increases. Therefore, the phase difference &phgr; shifts in the direction in which the rising change point of the input data matches the falling timing of the identification clock.
As described above, when the input data contains distortion, the phase synchronization means
1
does not involve a stable phase synchronization state as shown in FIG.
17
C. For input data distortion such that the logical high time becomes longer than the logical low time, the phase state makes a transition between
FIGS. 18A and 18C
. The phase transition becomes jitter in the identification clock output as a clock signal and the data signal identified by the identification means
5
and substantially lessens a phase margin in the identification means
5
. This is a problem in the clock reproduction and identification apparatus in the related art.
The operation of the phase synchronization means
1
has been described with reference to
FIGS. 17A
to
17
C by assuming that the input data is a “1, 0” pattern repetition signal and that the above-described phase synchronization loop functions for always synchronizing phases with each other at each change point of the input

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