Clock reproducing circuit for packet FSK signal receiver

Pulse or digital communications – Receivers – Angle modulation

Patent

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Details

375303, 375360, 375272, 329300, 329301, 329302, 329303, H03D 300, H04L 2706, H04L 702

Patent

active

059995777

ABSTRACT:
A circuit is provided by which in the case of the transmission of a short packet signal through an FSK transmission channel having a frequency error for transmission and reception, directly from one shaped rectangular pulse of a frequency detected bit synchronization signal having a DC offset (this pulse including a bias distortion as it is) a clock signal can be generated indicating the points of time when the base-band signal passes through its center level and the point of time when it arrives its maximum or minimum value (data sampling points of time). This invention utilizes the fact that the bit synchronization signal is in the form of a sine wave because it has been band limited. The sine wave including a DC offset is rectangularity shaped with respect to the zero axis as it is, and a counter is caused to start its counting operation by a raising-up or falling-down transition of this rectangular waveform and the count value of the counter is read out at the time of the falling-down or raising-up transition of the rectangular waveform. On the basis of the count value read out, the count values at a time when the base-band signal passed through its center level and the count value at a time when it arrives its maximum or minimum value (during the data section, a data sampling point of time) can be calculated directly. These calculated values are stored, and when the counter arrived these values, pulses are generated which are used to regenerate a clock.

REFERENCES:
patent: 4696016 (1987-09-01), Rozema et al.
patent: 5175544 (1992-12-01), McKeen
patent: 5267267 (1993-11-01), Kazawa et al.
patent: 5539784 (1996-07-01), Brauns et al.
patent: 5574748 (1996-11-01), Vander Mey et al.
patent: 5644600 (1997-07-01), Kawai

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