Clock reproducing circuit for eliminating an unnecessary spectru

Details Clock reproducing circuit for eliminating an unnecessary spectru Clock reproducing circuit for eliminating an unnecessary spectru

1992-03-17

1993-12-21

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural oscillators controlled

331 17, 331 25, H03L 707, H03L 7093

Patent

active

052724514

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

This invention relates to a clock reproducing or regenerating circuit for use in a pulse-width modulation (hereunder referred to as PWM) digital-to-analog (D/A) converter for the purpose of improving a signal-to-noise ratio (S/N) of the PWM D/A converter.


BACKGROUND ART

It has been a long time since equipments employing digital techniques had come to be put to practical use. In such an equipment, a D/A converter is used in a process in which a digital processing is performed on a digital quantity obtained as a result of a digitization of an analog quantity and thereafter another digital quantity representing the result of the digital processing is converted into another analog quantity. Heretofore, a D/A converter of what is called the resistance-ladder type, which is typified by an R-2R ladder D/A converter, has been used for such a purpose. Nowadays, integrated-circuit (IC) D/A converters have been developed with the intention of reducing costs. Increase in quantization number, however, results in rise of production costs of IC D/A converters for obtaining a desired conversion precision because of the fact that the conversion precision of an IC D/A converter depends on the accuracy of resistance of the internal circuit thereof. Recently, it has come to attempt to increase the conversion precision of a D/A converter by employing a PWM IC D/A circuit which can obtain a desired conversion precision independent of the accuracy of the resistance of the internal circuit thereof by utilizing a logic circuit thereof and employing PWM. However, with increase in conversion precision, the frequency of a fundamental clock input to the PWM D/A converter increases to the extent that no clocks supplied by a crystal oscillator for outputting a fundamental wave can have. Thus a frequency multiplier is employed therein as a countermeasure to such a problem.
However, lately, three kinds of equipments (namely, a compact-disk player (CD), a digital audio tape recorder (DAT) and a broadcasting-by-satellite (BS) tuner) respectively using different sampling frequencies have been put to practical use. As the result, a clock, the frequency of which is a specific multiple of the input sampling frequency, becomes necessary as a PCM clock. Further, it becomes necessary to change the frequency of a PWM clock according to the sampling frequency of an input signal, on which a D/A conversion should be performed. Furthermore, as described above, the frequency of a clock to be input to the PWM D/A converter becomes too high for the fundamental oscillation of a crystal oscillator to supply. Thus, a frequency multiplier employing a phase lock loop, another frequency multiplier utilizing what is called overtone oscillations and a frequency doubler utilizing an inductance or transformer (namely, a device for obtaining various frequencies, which are twice, triple or more the frequency of the fundamental oscillation, by utilizing parallel resonance achieved by means of an inductance and a capacity connected in parallel) have been proposed as means for obtaining higher clock frequencies. The frequency multiplier utilizing overtone oscillations and the frequency doubler, however, are unsuited for IC fabrication because they require inductive components. Consequently, the frequency multiplier employing a PLL is usually used. At that time, a spectrum of an unnecessary frequency component in case of performing a frequency division in a switching circuit, as well as a spectrum of another unnecessary frequency component occurring due to lead-lag filter characteristics of the frequency multiplier employing a PLL, is observed as illustrated in FIG. 1. Thus it turns out that the S/N of the PWM D/A converter is degraded due to the spectra of the unnecessary components. The results of a simulation of the manner of such degradation is described in an article entitled "Consideration on Clock Jitters in PWM D/A Converters", T. Kaneaki et al. (Matsushita Electric Industrial Co., Ltd. AV Research Laboratory), Kouen-Ronbun-Shu (in Japanese),

REFERENCES:
patent: 4180783 (1979-12-01), Khalifa
patent: 4806879 (1989-02-01), Troxel

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