Clock regenerator comprising a frequency divider controlled by a

Details Clock regenerator comprising a frequency divider controlled by a Clock regenerator comprising a frequency divider controlled by a

Filed on

1977-05-02

Date issued

1978-08-08

Examiner

Heyman, John S.

Other Related Categories

328 63, 328 74, 328134, 328 44, H03K 501, H03K 364

Type

Patent

Status

active

Patent number

041059794

Description

ABSTRACT:
A clock regenerator for an input data signal varying between a high and a low level at one or more bit periods comprises a controllable frequency divider for frequency dividing a local signal of a high frequency at a frequency division ratio into a regenerated clock signal. When the regenerated clock signal has a leading and a lagging phase difference relative to the input data signal, a counter preset once in every regenerated clock period with a reference value for the frequency division ratio up-counts and down-counts, respectively, the reference value as a function of the amount of the phase difference to control the frequency division ratio.

REFERENCES:
patent: 3671875 (1972-06-01), Pento
patent: 3781696 (1973-12-01), Van Loon et al.
patent: 3952254 (1976-04-01), Kurita et al.

Affiliated with

Also associated with

Rating

Clock regenerator comprising a frequency divider controlled by a does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock regenerator comprising a frequency divider controlled by a, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock regenerator comprising a frequency divider controlled by a will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-921950