Clock regeneration circuit employing digital phase locked loop

Details Clock regeneration circuit employing digital phase locked loop Clock regeneration circuit employing digital phase locked loop

1988-12-19

1990-01-09

Safourek, Benedict V.

Pulse or digital communications

Spread spectrum

Direct sequence

375119, 375120, 358148, H04L 704

Patent

active

048933198

ABSTRACT:
A clock regeneration circuit employing a digital phase locked loop for locking a video data signal to both a synchronization signal and a clock signal includes an oscillator for producing multiple phase clock signals, a synchronization latch circuit and a data latch circuit for selecting desired ones of the multiple phase clock signals, and a phase comparator for comparing the outputs of each of the latch circuits to produce an error signal which adjusts the phase of the synchronization signal to bring it into coincidence with the video data signal input. The phase adjusted synchronization signal controls the latching in the synchronization latch circuit and selects the appropriate phase of the multiple phase clock signals. In this way the horizontal synchronization pulses are locked to the video data and the locked horizontal synchronization pulses select a properly phased clock signal. In a matrix-addressed visual display, this ensures that the appropriate pixels are illuminated at the proper time.

REFERENCES:
patent: 4713691 (1987-12-01), Tanaka et al.

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