Pulse or digital communications – Spread spectrum – Direct sequence
Reexamination Certificate
1998-07-06
2002-02-05
Pham, Chi (Department: 2631)
Pulse or digital communications
Spread spectrum
Direct sequence
C375S147000
Reexamination Certificate
active
06345067
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a spread spectrum communication system, and in particular to a communication clock regenerating circuit using a direct spread passive type correlator.
In conventional data communications, communication schemes using a narrow band modulating system have been practically used. In these schemes, demodulation in a receiver can be implemented by a relatively compact circuit. However, it is susceptible to multi-path or narrow band non-white noise, which may occur in indoor environments such as offices or factories.
In contrast to this, the spread spectrum communication system has an advantage in that it can overcome the above-mentioned problems since a signal for carrying data thereon is transmitted in a wide band so that the spectrum of the signal to be transmitted is spread with a spread code when the signal is transmitted.
In such a system, a clock regenerating circuit is necessary to provide in a receiver a clock which is synchronized with the operation clock in a transmitter since both the transmitter and receiver are independently operated in response to different clocks. Such a clock regenerating circuit has conventionally comprised analog circuits, such as filtering circuits, VCO and shaping circuits. Since it is difficult to integrate analog circuits, resulting in problems with the circuit scale becoming larger and problems in circuit mounting due to coexistence of digital and analog circuits.
Hence, the inventor of the present application has invented a clock regenerating circuit which is formed of only digital circuits (refer to Japanese Laid-Open Patent Publication (TOKKAIHEI) No. 8-316875).
An example of this invention is shown in
FIGS. 1
to
3
.
FIG. 1
is a block diagram showing a circuit of the clock regenerating circuit, and
FIG. 2
is block diagram showing clock regenerating circuit in
FIG. 1
in more detail.
As shown in
FIG. 1
, a correlation signal which is obtained from a correlator (not shown) is extended along a time axis by delay elements
110
-
1
to
110
-
5
(for example, shift registers). At this time, sampling is conducted on a basis of two samples per chip.
The clock regeneration is carried out by a sync pulse, a window control unit
111
which is controlled by the sync pulse and a correlation signal for several samples which are gated by the window control unit
111
before and after the window.
The regenerating clock is generated based upon the sync pulse of a correlation sync circuit (not shown) . An offset in time between the clocks of the transmitter and the receiver is compensated for by means of a tracking circuit using the window. The correlation signal within a window (time window) is compared with a threshold value which is preset for each sample in comparators
112
-
1
to
112
-
5
so that it is output as a signal of “1” or “0”.
Thereafter, the output signals are added by means of adders
113
-
1
to
113
-
5
. A clock regenerating unit
115
is adapted to control the regenerating clock in the clock regenerating unit
115
in response to overflow signals from the adders if any.
FIG. 2
shows the details of the clock regenerating unit shown in FIG.
1
. In the clock regenerating unit
115
, the frequency of a sampling clock which is generated by a sync pulse generating circuit
115
g
and is used for despreading is divided by 2×k by means of a 2×k (k denotes the length of a spreading code) frequency divider
115
d
-
2
so that a data clock is generated. However, it is necessary to control the data clock since there is a clock offset in time between the transmitter and the receiver.
A method of controlling the clock will be described by way of a prior art with reference to FIG.
2
. If the adder
113
-
3
for the central timing in the window overflows first in an advance and lag control signal forming circuit
114
(refer to FIG.
1
), the clock regenerating unit
115
maintains the current timing. If an adder corresponding to early timing overflows first, the timing of the clock regenerating unit
115
is delayed by one sample (clock from a (2×k−1) frequency divider
115
d
-
1
is selected). If the later timing adder overflows first, the timing of the clock regenerating unit
115
is advanced by one sample (the clock from the (2×k+1) frequency divider
115
d
-
3
is selected). Tracking of the regenerating clock has been conventionally conducted in such a manner.
The relation of a correlation signal with respect to the regenerating clock timing in such operation is shown in FIG.
3
.
FIG. 3A
shows the synchronized timing relation. The current clock regenerating circuit is in a synchronization relationship with timing point
35
. In this case, timing point
35
occurs only when an ideal correlation signal exceeds a threshold. As a result, only adder
113
-
3
counts up in FIG.
1
.
Also in this case, a correlation signal may be deformed due to the influence of noise components. On an average, the adder
113
-
3
will count the most so that it overflows first. As a result, the clock regenerating timing determines that the timing relationship is correct and maintains its timing.
On the other hand,
FIG. 3B
shows the unsynchronized relationship. In this case, since the regenerated clock is delayed, the peak of the correlation signal is shifted by one period to the timing point
42
. As a result, the correlation signal exceeds the threshold at only the shifted timing point. As the result of this, only the adder
113
-
4
counts up by one.
Also in this case, the correlation signal may be deformed due to noise components. On an average, the adder
113
-
4
will count the most so that it overflows first. In this case, it is determined that the clock timing is late, so that it is advanced by one sample (a clock from the (2×k+1) frequency divider
115
d
-
3
is selected). Thus, the clock timing is shifted to timing point
35
so that correct clock timing is provided.
In such a conventional manner, the clock timing relationship is controlled so that the clock regeneration is achieved in the central position of the correlation. If, for example, the clock timing is offset between the transmitter and the receiver, an advancing operation is conducted every ½×k×100 seconds. Using the sampling timing for despreading the spread signal enables the clock regeneration to be digitally conducted.
The above-mentioned prior art (specification of Japanese Laid-Open Patent Publication (TOKKAIHEI) No. 8-316875 mentions a time window, weighting and threshold which is used for controlling the clock timing.
The inventor of the present application proposed a multiplexing system in spread spectrum technology in Japanese Laid-Open Patent Publication (TOKKAIHEI) No. 9-55714. Configuration of a transmitter system in the multiplexing system will be described with reference to
FIGS. 4A and 4B
.
A data signal from a data generator
121
is differentially encoded by means of a differential encoder
122
and is converted into four parallel signals P
1
through P
4
by means of a serial/parallel converter
123
. The parallel signals P
1
through P
4
are multiplied by a spread code from a PN generator
125
by means of multipliers
124
-
1
through
124
-
4
so that they become independent spread signals M
1
to M
4
. The spread signals are differently delayed by the delay elements
126
-
1
through
126
-
4
, and then combined with each other in a combiner
127
.The combined signal is modulated with a synthesized signal in a multi-value modulator
128
having an oscillator
129
, and is frequency-converted by a frequency converter
130
, and is then transmitted after it has been amplified by a power amplifier
131
. This causes a number of serial/parallel converted signals to be multiplexed and to be transmitted. Although conversion into four parallel signals is conducted in
FIG. 4
, the number of the converted parallel signals may be optionally determined on presetting of the multiplexing number.
A case in which the signal which has been transmitt
Burd Kevin M
Pham Chi
Sharp Kabushiki Kaisha
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