Clock recovery digital phase-locked loop

Details Clock recovery digital phase-locked loop Clock recovery digital phase-locked loop

1986-05-01

1987-07-14

Groody, James J.

Pulse or digital communications

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375 81, 375108, 331 1A, 328140, 328155, 329 2, 329 50, 329122, 329123, H03D 324, H03D 318

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046807802

ABSTRACT:
A digital phase-locked loop circuit for recovering an external clock signal from an input serial data stream includes an up/down counter responsive to both the serial data stream and to the clock pulse output of a variable divider driven by an external clock. The up/down counter counts in a direction which depends upon whether the input data stream leads or lags the variable divider's clock pulse output. The output of the up/down counter drives an n-bit memory and a comparator such that the n-bit memory stores the n most significant bits of the up/down counter for a predetermined period of time and then provides them to the comparator for comparison with the present value of the up/down counter. A binary code is provided to the variable divider to determine its divisor depending upon whether the memory count is greater than, equal to, or less than the present count of the up/down counter. This enables an external clock to be synchronized to the input data stream while removing random noise.

REFERENCES:
patent: 4019153 (1977-04-01), Cox, Jr. et al.
patent: 4119796 (1978-10-01), Jones
patent: 4280099 (1981-07-01), Rattlingourd
patent: 4330863 (1982-05-01), Wright
patent: 4374438 (1983-02-01), Crowley
"Digital Phase-Locked Loop Finds Clock Signal in Bit Stream"; by John Snyder, Electronics, vol. 52, No. 18, Aug. 30, 1979, pp. 126-130.

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