Pulse or digital communications – Synchronizers
Patent
1996-05-13
1997-12-30
Chin, Stephen
Pulse or digital communications
Synchronizers
330253, 330277, 330307, 330310, 327141, H04L 700
Patent
active
057039127
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The invention relates to a device for clock recovery from an input signal carrying alternating voltage and formed notably of a digital data signal, comprised of a frequency mixer to which on a first input a signal assigned the clock frequency of the alternating voltage-carrying input signal is fed, of a filter and an amplifier for amplification of a narrow-band frequency range of the output signal of the frequency mixer, with the filter and amplifier unit composed of the filter and amplifier possessing a high overall integrity, and of a feedback line for feeding the output signal of the amplifier to a second input of the frequency mixer.
Such a device is known from the article "MultiGbits/s Data Regeneration and Clock Recovery IC Design" by Zhigong Wang in the publication Annales des Telecommunications, volume 48, No. 3-4, which appeared in 1993, pages 132 through 147. This device features a flank detector with a monolithically integrated exclusive-or circuit XOR, with which the flanks of the alternating-voltage-carrying input signal allow detection via an exclusive-or comparison of two signal portions that are phase-shifted relative to each other and formed of the alternating-voltage-carrying input signal. The filter and amplifier function is carried out separately using an external falter with an integrity rating of about 600 and a monolithically integrated amplifier, the filter preferably fashioned as an acoustic surface wave filter.
The device features a limiter circuit for level adjustment of the output clock signal to a maximum value, said device following the amplifier. The output signal of the limiter circuit is fed to the second input of the frequency mixer via the feedback line. This device allows the regeneration of a clock signal from data signals at a data rate of about 3 gigabits per second. To raise the maximum feedable data transfer rate to 4.5 gigabits per second, three amplifiers succeed the filter in a modified configuration of this device.
In a second embodiment of the above device for clock recovery, the surface wave filter is replaced by a dielectric resonator filter, which is employed at a higher clock frequency, of about 10 gigahertz, so that the operating frequency can be increased as compared to a device incorporating a surface wave filter.
Although the above clock recovery devices have the advantage that the maximum feedable data rate can be doubled by tuning the center frequency of the filter to one-half the clock frequency of the data signal, the design of the filter as an external component of high integrity gives rise to three problems at data rates above 10 gigabits per second.
The first problem is that the surface wave filter and the dielectric resonator filter for a clock frequency above 5 gigahertz and an integrity rating of several hundred can be produced with the present state of the art only at a very high manufacturing expense. The second problem is that the asymmetric structure and the low-ohm inputs and outputs of both falter types prevent the realization of a stable overall circuit with a very high operating frequency. The third problem is that the hybrid structure of the overall circuit entails for a mass product a very high manufacturing expense with correspondingly high unit cost.
Known from the published article "New Proposal for a Multi-Gigabit/s Clock Recovery IC Based on a Standard Silicon Bipolar Technology," by Z. Wang and U. Langmann, in Electronics Letters 23 (1987) No. 9, pages 454, 455, is a clock recovery device where an external surface wave filter is provided in a feedback circuit between two band-pass amplifiers of monolithically integrated structure. The extracted frequency corresponds to one-half the clock frequency of the input signal fed to a frequency mixer. The overall integrity of a filter and amplifier unit formed of the two band-pass amplifiers and the interposed external filter is substantially determined by the relatively high integrity of the surface wave filter, since the band-pass amplifiers have an integr
REFERENCES:
patent: 5089789 (1992-02-01), Van Tran
Wang, "MultiGbits/s data regeneration and clock recovery IC design", Anna des telecommunications, Tome 48, No. 3-4, pp. 132-147, Apr. 1993.
Wang et al, "New Proposal for a Multigigabit/s Clock Recovery IC Based on a Standard Silicon Bipolar Technology", Electronic Letters, vol. 23, No. 9, pp. 454-455, Apr. 23, 1987.
Wang, "Monolithisch-Integrierte Silizium-Bipolar-Schaltungen Zur Taktruckgewinnung Bei Datenraten Von Mehreren Gbit/s", Dissertation, pp. 66-69 and 92-93, 1990.
Berroth Manfred
Wang Zhigong
Chin Stephen
Fraunhofer-Gesellschaft Zur Forderung der Angewandten Forschung
Phan Hai H.
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