Clock recovery control in differential detection

Details Clock recovery control in differential detection Clock recovery control in differential detection

1998-09-30

2001-07-31

Tse, Young T. (Department: 2734)

Pulse or digital communications

Receivers

Angle modulation

C375S327000, C375S376000, C327S159000, C327S160000, C329S341000

Reexamination Certificate

active

06269128

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a digital demodulator suitable for wireless digital communication equipment and, in particular to a clock recovery control technique for the digital demodulator employing differential detection.
2. Description of the Related Art
As well known, &pgr;/4-shift quadrature phase-shift keying (QPSK) is, simply described, a form of QPSK modulation in which the QPSK signal constellation is shifted by 45 degrees each symbol interval. Therefore, the phase transitions from one symbol to the next are restricted to ±&pgr;/4 and ±3&pgr;/4. Although the &pgr;/4-shift QPSK modulation can be implemented with coherent or differential detection, it is frequently implemented with differential detection because it is more simple, which is called differential &pgr;/4-shift QPSK, denoted simply as &pgr;/4-shift DQPSK. The &pgr;/4-shift DQPSK modulation scheme has been widely used for mobile communication equipment.
In such a conventional differential detector, however, when interference occurs, there are cases where a clock recovery circuit follows the interference wave, resulting in erroneous data decision.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a digital demodulator and a clock recovery control method that can provide reliable and stable clock regeneration even when interference occurs.
Another object of the present invention is to provide a digital demodulator that can perform precise differential detection.
The inventor has found that the erroneous data decision due to interference can be eliminated by changing a clock corrective width, or a clock tracking band width, of the clock recovery circuit depending on whether interference occurs.
According to an aspect of the present invention, a digital demodulator for demodulating a digital-modulated signal into received data using differential detection includes a level detector for detecting a received signal strength and a clock regenerator for regenerating a clock from the digital-modulated signal, wherein a phase of the clock is adjustable in steps of a clock corrective width. The digital demodulator further includes a variance calculator for calculating a variance of phase differences in the digital-modulated signal and a controller for controlling the clock corrective width of the clock regenerator based on the variance and the received signal strength.
Since the clock corrective width is controlled based on the variance and the received signal strength, reliable and stable clock recovery can be achieved even in the presence of interference.
The controller may determine whether interference occurs based on the variance and the received signal strength and control the clock corrective width depending on whether interference occurs. When it is determined that interference occurs, it is preferably that the clock corrective width is decreased.
The controller may determine whether the received signal strength is greater than a predetermined level and further whether the variance is greater than a predetermined value and then control the clock corrective width depending on a result of determination. When the result of determination is that the received signal strength is greater than the predetermined level and the variance is greater than the predetermined value, it is preferably that the clock corrective width is decreased.
According to another aspect of the present invention, the digital demodulator further includes a data detector for detecting that constant-value data is consecutively received for more than a predetermined time period. The controller controls the clock regenerator such that the phase of the clock is fixed when it has been detected that the constant-value data is consecutively received for more than the predetermined time period.
When the constant-value data is consecutively received for more than the predetermined time period, it can be determined that non-modulated interference occurs. In order to prevent the clock from being disturbed by the non-modulated interference, the phase of the clock is preferably fixed. In this manner, the clock phase correction control according to the present invention provides reliable and stable clock recovery even in the presence of modulated or non-modulated interference.


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