Clock recovery circuit with second order digital filter

Details Clock recovery circuit with second order digital filter Clock recovery circuit with second order digital filter

2006-10-24

2006-10-24

Bocure, Tesfaldet (Department: 2611)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C375S376000

Reexamination Certificate

active

07127017

ABSTRACT:
The present invention provides a method and mechanism for regenerating the clock signal and recovering the data of a serial bit data stream. According to an embodiment, a circuit for recovering data from a serial bit stream may include a de-serializer configured for reclocking the serial bit stream using at least one reclocking signal, having a frequency with a phase, and de-serializing the serial bit stream into at least two bit streams. The circuit may further include a clock recovery loop filter having a second order filter coupled with the deserializer. The clock recovery loop filter may be configured for determining whether the de-serializer is reclocking the serial bit data stream at an optimum location and for generating at least one control signal to adjust the phase of the frequency of the at least one reclocking signal if the de-serializer is not reclocking the serial bit data stream at the optimum location. The circuit may also include a phase interpolator coupled with the clock recovery loop filter and the de-serializer, configured for generating the at least one reclocking signal in accordance with the at least one control signal.

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