Clock recovery circuit with reduced jitter

Details Clock recovery circuit with reduced jitter Clock recovery circuit with reduced jitter

1995-06-01

1997-08-05

Chin, Stephen

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

375354, 375376, 375294, H04L 700

Patent

active

056549873

ABSTRACT:
A clock recovery circuit has at least two comparators that detect timings at which a digitally modulated signal crosses different levels, and generate level crossing signals at these timings. A classifying circuit classifies sequences of these level crossing signals and issues corresponding classification signals. A timing control circuit generates timing pulses from certain combinations of the level crossing signals and classification signals. A digital phase-locked loop outputs a clock signal synchronized to these timing pulses.

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patent: 4651026 (1987-03-01), Serfaty et al.
patent: 4700357 (1987-10-01), Ast
patent: 5121411 (1992-06-01), Fluharty
patent: 5297173 (1994-03-01), Hikmet et al.
patent: 5537442 (1996-07-01), Nakamura
Akaiwa and Nagata, "A Linear Modulation Scheme for Digital Mobile Radio Communications", CH2190-7/85/0000-0965, IEEE, 1985.
Nobuta et al., ".pi./4-shift QPSK Differential Demodulator for Digital Cordless Telephone", Papers from the 1992 Spring Meeting of the Institute of Electronics, Communication, and Information Engineers of Japan.

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