Clock recovery circuit with open-loop phase estimator and wideba

Details Clock recovery circuit with open-loop phase estimator and wideba Clock recovery circuit with open-loop phase estimator and wideba

1991-06-25

1993-08-10

Kuntz, Curtis

Pulse or digital communications

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375 79, 375 81, 375120, 329306, 329307, 455 60, 455265, H04L 7027

Patent

active

052356221

ABSTRACT:
In a clock recovery circuit, a received APSK signal is sampled at a frequency N times higher than the transmitted clock in response to a first clock from a local clock source, and quantized into orthogonal digital APSK samples. An envelope of the orthogonal APSK digital samples is detected (3) and phase correlations are detected (5) between the envelope and locally generated orthogonal sinusoidal signals and averaged by a low-pass filter (6). The arctangent between the low-pass filtered orthogonal signals is detected (7) and applied to a subtracter (8). A threshold comparator (9) compares the subtracter output with N successive values. A digital V.C.O. (10) is supplied with an output signal from the comparator (9) to generate a sample clock f.sub.c at a frequency 1/N of the frequency of the first clock f.sub.s for sampling the digital samples from the A/D converter (1). A phase difference is detected by a phase comparator (12) between the second clock f.sub.c and the sample clock f.sub.c, the phase difference being applied to the subtracter (8) in which the difference between it and the arctangent is determined. The V.C.O. (10) controls the timing of the sample clock in response to the first clock f.sub.s in accordance with the output of the threshold comparator (9).

REFERENCES:
patent: 4516079 (1985-05-01), York
patent: 4672447 (1987-06-01), Moring et al.
patent: 4847880 (1989-07-01), Kamerman et al.
patent: 5065412 (1991-11-01), Schenk
Preambleless Demodulator For Satellite Communications; H. Tomita and J. Namiki, C&C Systems Research Labs., NEC Corporation, 1989 IEEE, pp. 16.4.1-16.4.5.

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