Clock recovery circuit of demodulator

Details Clock recovery circuit of demodulator Clock recovery circuit of demodulator

1996-02-12

1997-06-17

Tse, Young T.

Pulse or digital communications

Receivers

Angle modulation

329306, H04L 2722

Patent

active

056404263

ABSTRACT:
A clock recovery circuit capable of outputting decision point data without causing any slip of a recovered clock in the case of operation in a continuous mode in a demodulator in which received signals are sampled by a fixed frequency clock to obtain the recovered clock and symbol data are demodulated by using this recovered clock. A shift register stores digital received signals obtained by an A/D conversion of quasi-coherent detection received signals, and a clock phase estimator calculates an estimated phase difference between an output value of a phase generator operated by the fixed frequency clock and a symbol clock of the received signals and outputs timing information and phase information of a decision point for discriminating the data of the received signals. An interpolator inputs the output signal of the clock phase estimator, takes in the digital received signals from the shift register and calculates decision point data by interpolation to output the same. The interpolator operates at the same cycle as the symbol clock on an average.

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Shousei Yoshida, Hideho Tomita "A New Coherent Demodulation Technique for Land-Mobile Satellite Communications; International Mobile Satellite Conference", Ottawa, 1990.
L.P. Sabel and W.G. Cowley, "A Recursive Algorithm for the Estimation of Symbol Timing in PSK Burst Modems:, IEEE Global Telecommunications Conf.", vol. 1, 9 Dec. 1992, Orlando, FL, pp. 360-364.

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